Datasheet
AD9522-1
Rev. 0 | Page 17 of 84
NOTES
1. EXPOSED DIE PAD MUST BE CONNECTED TO GND.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SDIO/SDA
SDO
GND
SP1
SP0
EEPROM
RESET
PD
T9 (OUT9A)
T9 (OUT9B)
VS
OUT10A)
OUT10B)
OUT11A)
OUT11B)
VS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
REFIN (REF1)
REFIN (REF2)
CPRSET
VS
VS
GND
RSET
VS
OUT0 (OUT0A)
OUT0 (OUT0B)
VS
OUT1 (OUT1A)
OUT1 (OUT1B)
OUT2 (OUT2A)
OUT2 (OUT2B)
VS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VS
REFMON
LD
VCP
CP
STATUS
REF_SEL
SYNC
LF
BYPASS
VS
VS
CLK
CLK
CS
OU
OU
OUT10 (
OUT10 (
OUT11 (
OUT11 (
S
CLK/SCL
OUT3 (OUT3A)
OUT3 (OUT3B)
VS
OUT4 (OUT4A)
OUT4 (OUT4B)
OUT5 (OUT5A)
OUT5 (OUT5B)
VS
VS
OUT8 (OUT8B)
OUT8 (OUT8A)
OUT7 (OUT7B)
OUT7 (OUT7A)
VS
OUT6 (OUT6B)
OUT6 (OUT6A)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD9522
TOP VIEW
(Not to Scale)
07220-003
Figure 5. Pin Configuration
Table 21. Pin Function Descriptions
Pin No.
Input/
Output
Pin
Type Mnemonic Description
1, 11, 12, 27,
32, 35, 40,
41, 46, 49,
54, 57, 60, 61
I Power VS 3.3 V Power Pins.
2 O 3.3 V CMOS REFMON Reference Monitor (Output). This pin has multiple selectable outputs.
3 O 3.3 V CMOS LD
Lock Detect (Output). This pin has multiple selectable outputs.
4 I Power VCP
Power Supply for Charge Pump (CP); VS ≤ VCP ≤ 5.25 V. VCP must still be connected
to 3.3 V if the PLL is not used.
5 O Loop filter CP
Charge Pump (Output). This pin connects to an external loop filter. This pin can
be left unconnected if the PLL is not used.
6 O 3.3 V CMOS STATUS
Programmable Status Output.
7 I 3.3 V CMOS REF_SEL
Reference Select. It selects REF1 (low) or REF2 (high). This pin has an internal
30 kΩ pull-down resistor.
8 I 3.3 V CMOS
SYNC
Manual Synchronizations and Manual Holdover. This pin initiates a manual
synchronization and is used for manual holdover. Active low. This pin has an
internal 30 kΩ pull-up resistor.
9 I Loop filter LF
Loop Filter (Input). It connects internally to the VCO control voltage node.
10 O Loop filter BYPASS
This pin is for bypassing the LDO to ground with a 220 nF capacitor.
This pin can be left unconnected if the PLL is not used.
Along with CLK
, this pin is the differential input for the clock distribution section.
13 I
Differential
clock input
CLK
14 I
Differential
clock input
CLK
Along with CLK, this pin is the differential input for the clock distribution section. If a
single-ended input is connected to the CLK pin, connect a 0.1 μF bypass capacitor
from this pin to ground.