Datasheet

AD9522-1
Rev. 0 | Page 14 of 84
PD, SYNC, AND RESET PINS
Table 15.
Parameter Min Typ Max Unit Test Conditions/Comments
INPUT CHARACTERISTICS Each of these pins has an internal 30 kΩ pull-up resistor
Logic 1 Voltage 2.0 V
Logic 0 Voltage 0.8 V
Logic 1 Current 1 μA
Logic 0 Current −110 μA
The minus sign indicates that current is flowing out of
the AD9522, which is due to the internal pull-up resistor
Capacitance 2 pF
RESET TIMING
Pulse Width Low 50 ns
RESET Inactive to Start of Register Programming
100 ns
SYNC TIMING
Pulse Width Low 1.3 ns High speed clock is CLK input signal
SERIAL PORT SETUP PINS: SP1, SP0
Table 16.
Parameter Min Typ Max Unit Test Conditions/Comments
SP1, SP0 These pins do not have internal pull-up/pull-down resistors
Logic Level 0 0.25 × VS V VS is the voltage on the VS pin
Logic Level ½ 0.4 × VS 0.65 × VS V
User can float these pins to obtain Logic Level ½; if floating this pin, user
should connect a capacitor to ground
Logic Level 1 0.8 × VS V
LD, STATUS, AND REFMON PINS
Table 17.
Parameter Min Typ Max Unit Test Conditions/Comments
OUTPUT CHARACTERISTICS
When selected as a digital output (CMOS); there are other
modes in which these pins are not CMOS digital outputs;
see Table 52, 0x017, 0x01A, and 0x01B
Output Voltage High, V
OH
2.7 V
Output Voltage Low, V
OL
0.4 V
MAXIMUM TOGGLE RATE 100 MHz
Applies when mux is set to any divider or counter output,
or PFD up/down pulse; also applies in analog lock detect
mode; usually debug mode only; note that spurs can
couple to output when any of these pins are toggling
ANALOG LOCK DETECT
Capacitance 3 pF
On-chip capacitance; used to calculate RC time constant
for analog lock detect readback; use a pull-up resistor
REF1, REF2, AND VCO FREQUENCY STATUS MONITOR
Normal Range 1.02 MHz
Frequency above which the monitor indicates the
presence of the reference
Extended Range 8 kHz
Frequency above which the monitor indicates the
presence of the reference
LD PIN COMPARATOR
Trip Point 1.6 V
Hysteresis 260 mV