Datasheet

AD9522-1
Rev. 0 | Page 13 of 84
SERIAL CONTROL PORT—I²C MODE
Table 14.
Parameter Min Typ Max Unit Test Conditions/Comments
SDA, SCL (WHEN INPUTTING DATA)
Input Logic 1 Voltage 0.7 × VS V
Input Logic 0 Voltage 0.3 × VS V
Input Current with an Input Voltage Between
0.1 × VS and 0.9 × VS
−10 +10 μA
Hysteresis of Schmitt Trigger Inputs 0.015 × VS V
Pulse Width of Spikes That Must Be Suppressed by
the Input Filter, t
SPIKE
50 ns
SDA (WHEN OUTPUTTING DATA)
Output Logic 0 Voltage at 3 mA Sink Current 0.4 V
Output Fall Time from VIH
MIN
to VIL
MAX
with a Bus
Capacitance from 10 pF to 400 pF
20 + 0.1 C
b
250 ns C
b
= capacitance of one bus line in pF
TIMING
Note that all I
2
C timing values refer
to VIH
MIN
(0.3 × VS) and VIL
MAX
levels
(0.7 × VS)
Clock Rate (SCL, f
I2C
) 400 kHz
Bus Free Time Between a Stop and Start Condition, t
IDLE
1.3 μs
Setup Time for a Repeated Start Condition, t
SET; STR
0.6 μs
Hold Time (Repeated) Start Condition (After This Period,
the First Clock Pulse Is Generated), t
HLD; STR
0.6 μs
Setup Time for Stop Condition, t
SET; STP
0.6 μs
Low Period of the SCL Clock, t
LOW
1.3 μs
High Period of the SCL Clock, t
HIGH
0.6 μs
SCL, SDA Rise Time, t
RISE
20 + 0.1 C
b
300 ns C
b
= capacitance of one bus line in pF
SCL, SDA Fall Time, t
FALL
20 + 0.1 C
b
300 ns C
b
= capacitance of one bus line in pF
Data Setup Time, t
SET; DAT
120 ns
This is a minor deviation from the
original I²C specification of 100 ns
minimum
Data Hold Time, t
HLD; DAT
140 880 ns
This is a minor deviation from the
original I²C specification of 0 ns
minimum
1
Capacitive Load for Each Bus Line, C
b
400 pF
1
According to the original I
2
C specification, an I
2
C master must also provide a minimum hold time of 300 ns for the SDA signal to bridge the undefined region of the SCL
falling edge.