Datasheet

AD9520-5 Data Sheet
Rev. A | Page 60 of 76
Reg.
Addr.
(Hex)
Bits Name Description
[2:0] Prescaler P Prescaler: DM = dual modulus and FD = fixed divide. The Prescaler P is part of the feedback divider.
Bit
2
Bit
1
Bit
0
Mode Prescaler
0 0 0 FD Divide-by-1.
0 0 1 FD Divide-by-2.
0 1 0 DM Divide-by-2 and divide-by-3 when A ≠ 0; divide-by-2 when A = 0.
0 1 1 DM Divide-by-4 and divide-by-5 when A ≠ 0; divide-by-4 when A = 0.
1 0 0 DM Divide-by-8 and divide-by-9 when A ≠ 0; divide-by-8 when A = 0.
1 0 1 DM Divide-by-16 and divide-by-17 when A ≠ 0; divide-by-16 when A = 0.
1 1 0 DM Divide-by-32 and divide-by-33 when A ≠ 0; divide-by-32 when A = 0 (default).
1 1 1 FD Divide-by-3.
0x017 [7:2]
STATUS
pin control
Selects the signal that appears at the STATUS pin. Register 0x01D[7] must be 0 to reprogram the STATUS pin.
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Level or
Dynamic
Signal Signal at STATUS Pin
0 0 0 0 0 0 LVL Ground, dc (default).
0 0 0 0 0 1 DYN N divider output (after the delay).
0 0 0 0 1 0 DYN R divider output (after the delay).
0 0 0 0 1 1 DYN A divider output.
0 0 0 1 0 0 DYN Prescaler output.
0 0 0 1 0 1 DYN PFD up pulse.
0 0 0 1 1 0 DYN PFD down pulse.
0 X X X X X LVL Ground (dc). Used for all settings of these bits not otherwise specified in this table.
The selections that follow are also used for REFMON and LD pin control.
1 0 0 0 0 0 LVL Ground (dc).
1 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode).
1 0 0 0 1 0 DYN REF2 clock (N/A in differential mode).
1 0 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode).
1 0 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode).
1 0 0 1 0 1 LVL Status of selected reference (status of differential reference); active high.
1
0
0
1
1
0
LVL
Status of unselected reference (not available in differential mode); active high.
1 0 0 1 1 1 LVL Status of REF1 frequency; active high.
1 0 1 0 0 0 LVL Status of REF2 frequency; active high.
1 0 1 0 0 1 LVL (Status of REF1 frequency) AND (status of REF2 frequency).
1 0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of CLK).
1 0 1 0 1 1 LVL Status of CLK frequency; active high.
1 0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2).
1 0 1 1 0 1 LVL DLD; active high.
1 0 1 1 1 0 LVL Holdover active; active high.
1 0 1 1 1 1 LVL N/A. Do not use.
1 1 0 0 0 0 LVL Vs (PLL power supply).
1 1 0 0 0 1 DYN
REF1 clock
(differential reference when in differential mode).
1 1 0 0 1 0 DYN
REF2 clock
(not available in differential mode).
1 1 0 0 1 1 DYN
Selected reference to PLL
(differential reference when in differential mode).
1 1 0 1 0 0 DYN
Unselected reference to PLL
(not available when in differential mode).
1 1 0 1 0 1 LVL Status of selected reference (status of differential reference); active low.
1 1 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active low.
1 1 0 1 1 1 LVL Status of REF1 frequency; active low.
1 1 1 0 0 0 LVL Status of REF2 frequency; active low.
1 1 1 0 0 1 LVL
(Status of REF1 frequency) AND (status of REF2 frequency)
.
1 1 1 0 1 0 LVL
(DLD) AND (status of selected reference) AND (status of VCO)
.
1 1 1 0 1 1 LVL Status of CLK frequency; active low.
1 1 1 1 0 0 LVL Selected reference (low = REF2, high = REF1).
1 1 1 1 0 1 LVL DLD; active low.
1 1 1 1 1 0 LVL Holdover active; active low.
1 1 1 1 1 1 LVL N/A. Do not use.