Datasheet

Data Sheet AD9520-5
Rev. A | Page 55 of 76
REGISTER MAP
Register addresses that are not listed in Table 44 are not used, and writing to those registers has no effect. Writing to register addresses
that are marked as unused also has no effect.
Table 44. Register Map Overview
Addr.
(Hex)
Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
Default
Value
(Hex)
Serial Port Configuration
0x000 Serial port
config
(SPI mode)
SDO active LSB first/
addr incr
Soft reset
(self-clear)
Unused Unused Soft reset
(self-clear)
LSB first/addr incr SDO active 0x00
Serial port
config
(I²C mode)
Unused Soft reset
(self-clear)
Unused Unused Soft reset
(self-clear)
Unused 0x00
0x001 Unused Unused N/A
0x002 Reserved Reserved N/A
0x003 Part ID Part ID (read only) 0x20
0x004 Readback
control
Unused Read back
active regs
0x00
EEPROM ID
0x005 EEPROM
customer
version ID
EEPROM customer version ID (LSB) 0x00
0x006 EEPROM customer version ID (MSB) 0x00
0x007
to
0x00F
Unused Unused 0x00
PLL
0x010 PFD charge
pump
PFD polarity Charge pump current Charge pump mode PLL power-down 0x7D
0x011
R counter
14-bit R counter, Bits[7:0] (LSB) 0x01
0x012 Unused 14-bit R counter, Bits[13:8] (MSB) 0x00
0x013 A counter Unused 6-bit A counter 0x00
0x014
B counter
13-bit B counter, Bits[7:0] (LSB) 0x03
0x015 Unused 13-bit B counter, Bits[12:8] (MSB) 0x00
0x016 PLL_CTRL_1 Set CP pin
to V
CP
/2
Reset
R counter
Reset
A and B
counters
Reset all
counters
B counter
bypass
Prescaler P 0x06
0x017 PLL_CTRL_2 STATUS pin control Antibacklash pulse width 0x00
0x018
PLL_CTRL_3
Enable CMOS
reference input
dc offset
Lock detect counter
Digital lock
detect
window
Disable digital
lock detect
Unused
0x06
0x019 PLL_CTRL_4 R, A, and B counters
SYNC
pin reset
R path delay N path delay 0x00
0x01A PLL_CTRL_5 Enable
STATUS pin
divider
Ref freq
monitor
threshold
LD pin control 0x00
0x01B PLL_CTRL_6 Enable CLK
frequency
monitor
Enable REF2
(
REFIN
)
frequency
monitor
Enable
REF1
(REFIN)
frequency
monitor
REFMON pin control 0x00
0x01C PLL_CTRL_7 Disable
switchover
deglitch
Select REF2 Use
REF_SEL
pin
Enable
automatic
reference
switchover
Stay on REF2 Enable
REF2
Enable
REF1
Enable
differential
reference
0x00
0x01D
PLL_CTRL_8
Enable
STATUS_EEPROM
at STATUS pin
Enable
XTAL OSC
Enable
clock
doubler
Disable
PLL status
register
Enable LD pin
comparator
Unused
Enable
external holdover
Enable
holdover
0x80
0x01E
PLL_CTRL_9
Unused
Enable
zero delay
Unused
0x00
0x01F PLL_Readback
(read only)
Unused Holdover
active
REF2
selected
CLK
freq > threshold
REF2
freq >
threshold
REF1 freq >
threshold
Digital lock
detect
N/A