Datasheet

Data Sheet AD9520-5
Rev. A | Page 37 of 76
Figure 37. Zero Delay Function
ZERO DELAY OPERATION
Zero delay operation aligns the phase of the output clocks with
the phase of the external PLL reference input.
The zero delay function of the AD9520-5 is achieved by feeding
the output of Channel Divider 0 back to the PLL N divider. In
Figure 37, the change in signal routing for zero delay mode is
shown in blue.
Set Register 0x01E[1] = 1b to select zero delay mode. In the zero
delay mode, the output of Channel Divider 0 is routed back to the
PLL (N divider) through Mux1 (feedback path shown in blue in
Figure 37). The PLL synchronizes the phase/edge of the output of
Channel Divider 0 with the phase/edge of the reference input.
Because the channel dividers are synchronized to each other,
the outputs of the channel divider are synchronous with the
reference input. Both the R delay and the N delay inside the
PLL can be programmed to compensate for the propagation
delay from the output drivers and PLL components to minimize
the phase offset between the clock output and the reference
input to achieve zero delay.
DIVIDE BY 1,
2, 3, 4, 5, OR 6
EXTERNAL VCXO
CLK/CLK
R
DIVIDER
R
DELAY
N
DIVIDER
N
DELAY
PFD
CP
MUX1
REG 0x01E[1] = 1
01
REFIN/
REFIN
INTERNAL ZERO DELAY CLOCK FEEDBACK PATH
CHANNEL DIVIDER 0
CHANNEL DIVIDER 1
CHANNEL DIVIDER 2
CHANNEL DIVIDER 3
OUT0 TO OUT2
OUT3 TO OUT5
OUT6 TO OUT8
OUT9 TO OUT11
AD9520-5
07239-053
LOOP
FILTER