Datasheet

Data Sheet AD9520-4
Rev. A | Page 65 of 80
Table 54. PLL
Reg.
Addr.
(Hex)
Bits Name Description
0x010 7 PFD polarity
Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO only.
The on-chip VCO requires positive polarity; Bit 7 = 0b.
0: positive (higher control voltage produces higher frequency) (default).
1: negative (higher control voltage produces lower frequency).
[6:4] CP current Charge pump current (with CP
RSET
= 5.1 kΩ).
Bit
6
Bit
5
Bit
4
I
CP
(mA)
0 0 0 0.6
0 0 1 1.2
0
1
0
1.8
0 1 1 2.4
1
0
0
3.0
1 0 1 3.6
1 1 0 4.2
1 1 1 4.8 (default)
[3:2] CP mode Charge pump operating mode.
Bit
3
Bit
2
Charge Pump Mode
0 0 High impedance state
0 1 Forces source current (pump up)
1 0 Forces sink current (pump down)
1 1 Normal operation (default)
[1:0] PLL power-down PLL operating mode.
Bit
1
Bit
0
Mode
0 0 Normal operation; this mode must be selected to use the PLL
0 1 Asynchronous power-down (default)
1 0 Unused
1 1 Synchronous power-down
0x011 [7:0]
14-bit R counter,
Bits[7:0] (LSB)
Reference divider LSBs—lower eight bits. The reference divider (also called the R divider or R counter) is 14 bits long.
The lower eight bits are in this register (default: 0x01).
0x012 [7:6] Unused Unused.
[5:0]
14-bit R counter,
Bits[13:8] (MSB)
Reference divider MSBs—upper six bits. The reference divider (also called the R divider or R counter) is 14 bits long.
The upper six bits are in this register (default: 0x00).
0x013 [7:6] Unused Unused.
[5:0] 6-bit A counter A counter (part of N divider). The N divider is also called the feedback divider (default: 0x00).
0x014 [7:0]
13-bit B counter,
Bits[7:0] (LSB)
B counter (part of N divider)—lower eight bits. The N divider is also called the feedback divider (default: 0x03).
0x015 [7:5] Unused Unused.
[4:0]
13-bit B counter,
Bits[12:8] (MSB)
B counter (part of N divider)—upper five bits. The N divider is also called the feedback divider (default: 0x00).
0x016 7
Set CP pin
to V
CP
/2
Sets the CP pin to one-half of the V
CP
supply voltage.
0: CP normal operation (default).
1: CP pin set to V
CP
/2.
6 Reset R counter
Resets R counter (R divider).
0: normal (default).
1: holds R counter in reset.
5
Reset A and B
counters
Resets A and B counters (part of N divider).
0: normal (default).
1: holds A and B counters in reset.
4
Reset all
counters
Resets R, A, and B counters.
0: normal (default).
1: holds R, A, and B counters in reset.
3 B counter bypass
B counter bypass. This is valid only when operating the prescaler in FD mode.
0: normal (default).
1: B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for the N divider.