Datasheet

Data Sheet AD9520-3
Rev. A | Page 9 of 80
Timing Diagrams
DIFFERENTIAL
LVPECL
80%
20%
t
RP
t
FP
07216-061
Figure 2. LVPECL Timing, Differential
CLK
t
CMOS
t
CLK
t
PECL
07216-060
Figure 3. CLK/
CLK
to Clock Output Timing, DIV = 1
SINGLE-ENDED
CMOS
10pF LOAD
80%
20%
t
RC
t
FC
07216-063
Figure 4. CMOS Timing, Single-Ended, 10 pF Load