Datasheet

Data Sheet AD9520-3
Rev. A | Page 5 of 80
Parameter Min Typ Max Unit Test Conditions/Comments
Pulse Width High/Low 1.8 ns The amount of time that a square wave is high/low;
determines the allowable input duty cycle
Crystal Oscillator
Crystal Resonator Frequency Range 16.62 33.33 MHz
Maximum Crystal Motional Resistance 30 Ω
PHASE/FREQUENCY DETECTOR (PFD)
PFD Input Frequency 100 MHz Antibacklash pulse width = 1.3 ns
45 MHz Antibacklash pulse width = 2.9 ns
Reference Input Clock Doubler Frequency 0.004 50 MHz
Antibacklash Pulse Width 1.3 ns Register 0x017[1:0] = 01b
2.9 ns Register 0x017[1:0] = 00b; Register 0x017[1:0] = 11b
6.0 ns Register 0x017[1:0] = 10b
CHARGE PUMP (CP)
CP
V
is the CP pin voltage; V
CP
is the charge pump power
supply voltage (VCP pin)
I
CP
Sink/Source Programmable
High Value 4.8 mA With CP
RSET
= 5.1 kΩ; higher I
CP
is possible by changing
CP
RSET
Low Value 0.60 mA With CP
RSET
= 5.1 kΩ; lower I
CP
is possible by changing
CP
RSET
Absolute Accuracy 2.5 % CP
V
= V
CP
/2
CPRSET Range 2.7 10 kΩ
I
CP
High Impedance Mode Leakage 1 nA
Sink-and-Source Current Matching 1 % 0.5 V < CP
V
< V
CP
− 0.5 V; CP
V
is the CP pin voltage;
V
CP
is the charge pump power supply voltage (VCP pin)
I
CP
vs. V
CP
1.5 % 0.5 V < CP
V
< V
CP
− 0.5 V
I
CP
vs. Temperature
2
%
CP
V
= V
CP
/2
PRESCALER (PART OF N DIVIDER)
Prescaler Input Frequency
P = 1 FD 300 MHz
P = 2 FD
600
MHz
P = 3 FD 900 MHz
P = 2 DM (2/3) 200 MHz
P = 4 DM (4/5) 1000 MHz
P = 8 DM (8/9) 2400 MHz
P = 16 DM (16/17)
3000
MHz
P = 32 DM (32/33) 3000 MHz
Prescaler Output Frequency 300 MHz A, B counter input frequency (prescaler input
frequency divided by P)
PLL N DIVIDER DELAY Register 0x019[2:0]; see Table 54
000 Off
001 385 ps
010 486 ps
011 623 ps
100
730
ps
101 852 ps
110 976 ps
111 1101 ps
PLL R DIVIDER DELAY
Register 0x019[5:3]; see Table 54
000 Off
001 365 ps
010 486 ps
011 608 ps
100 730 ps
101 852 ps
110 976 ps
111 1101 ps