Datasheet

Data Sheet AD9520-3
Rev. A | Page 15 of 80
PD
, EEPROM,
RESET
, AND
SYNC
PINS
Table 15.
Parameter Min Typ Max Unit Test Conditions/Comments
INPUT CHARACTERISTICS
Each pin has a 30 kΩ internal pull-up resistor
Logic 1 Voltage 2.0 V
Logic 0 Voltage 0.8 V
Logic 1 Current 1 µA
Logic 0 Current −110 µA The minus sign indicates that current is flowing out of
the AD9520, which is due to the internal pull-up resistor
Capacitance
2
pF
RESET TIMING
Pulse Width Low
500
ns
RESET
Inactive to Start of Register
Programming
100 ns
SYNC
TIMING
Pulse Width Low 1.3 ns High speed clock is CLK input signal
SERIAL PORT SETUP PINS—SP1, SP0
Table 16.
Parameter Min Typ Max Unit Test Conditions/Comments
SP1, SP0
These pins do not have internal pull-up/pull-down
resistors
Logic Level 0 0.25 × V
S
V V
S
is the voltage on the VS pin
Logic Level ½ 0.4 × V
S
0.65 × V
S
V These pins can be floated to obtain Logic Level ½; if
floating the pin, connect a capacitor to ground
Logic Level 1 0.8 × V
S
V
LD, STATUS, AND REFMON PINS
Table 17.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
OUTPUT CHARACTERISTICS When selected as a digital output (CMOS); there are
other modes in which these pins are not CMOS digital
outputs; see Table 54, Register 0x017, Register 0x01A,
and Register 0x01B
Output Voltage High, V
OH
2.7 V
Output Voltage Low, V
OL
0.4 V
MAXIMUM TOGGLE RATE 100 MHz Applies when mux is set to any divider or counter output
or PFD up/down pulse; also applies in analog lock detect
mode; usually debug mode only; beware that spurs can
couple to output when any pin is toggling
ANALOG LOCK DETECT
Capacitance 3 pF On-chip capacitance; used to calculate RC time constant
for analog lock detect readback; use a pull-up resistor
REF1, REF2, AND VCO FREQUENCY
STATUS MONITOR
Normal Range
1.02
MHz
Frequency above which the monitor indicates the
presence of the reference
Extended Range 8 kHz Frequency above which the monitor indicates the
presence of the reference
LD PIN COMPARATOR
Trip Point 1.6 V
Hysteresis 260 mV