Datasheet

Data Sheet AD9520-3
Rev. A | Page 13 of 80
SERIAL CONTROL PORT—SPI MODE
Table 13.
Parameter Min Typ Max Unit Test Conditions/Comments
CS
(INPUT)
CS
has an internal 30 kΩ pull-up resistor
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current 3 µA
Input Logic 0 Current −110 µA The minus sign indicates that current is flowing
out of the AD9520, which is due to the internal
pull-up resistor
Input Capacitance 2 pF
SCLK (INPUT IN SPI MODE) SCLK has an internal 30 kΩ pull-down resistor in
SPI mode but not in I
2
C mode
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current 110 µA
Input Logic 0 Current
1
µA
Input Capacitance 2 pF
SDIO (INPUT IN BIDIRECTIONAL MODE)
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current 1 µA
Input Logic 0 Current 1 µA
Input Capacitance 2 pF
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage 2.7 V
Output Logic 0 Voltage 0.4 V
TIMING
Clock Rate (SCLK, 1/t
SCLK
) 25 MHz
Pulse Width High, t
HIGH
16 ns
Pulse Width Low, t
LOW
16 ns
SDIO to SCLK Setup, t
DS
4 ns
SCLK to SDIO Hold, t
DH
0 ns
SCLK to Valid SDIO and SDO, t
DV
11 ns
CS
to SCLK Setup and Hold, t
S
, t
C
2 ns
CS
Minimum Pulse Width High, t
PWH
3 ns