Datasheet

UG-076 Evaluation Board User Guide
Rev. 0 | Page 14 of 16
AD9520 PLL LOOP FILTER
The AD9520 PLL requires an external loop filter whose
components are tailored for different applications. The third-
order passive configuration shown in Figure 27 usually offers
the best performance for many applications and is the one
found on the evaluation board.
LF
VCO
CHARGE
PUMP
CP
BYPASS
C1 C2 C3
R1
R2
C
BP
= 220nF
AD9520
0
8746-021
Figure 27. PLL Loop Filter
The default loop filter on the AD9520 evaluation board is
optimized for reference clock cleanup. It has a flat transfer
function with peaking <0.1 dB and loop bandwidths from
0.5 kHz to 10 kHz. In most of these applications, the phase
detector is run at 1 MHz or less.
In the example in the Quick Start Guide to the AD9520 PLL
section, the default loop filter shown in Table 2 results in a PLL
with a loop bandwidth of 2.2 kHz, 80° of phase margin, and
0.05 dB of peaking. The charge pump current for this example
is 1.2 mA.
For clock generation applications in which the reference clock is
relatively low jitter, the high loop bandwidth (BW) loop filter
shown in Table 2 is a better choice. Typical phase detector
frequencies for these applications are 10 MHz to 100 MHz,
and typical loop bandwidths for this loop filter are 50 kHz to
500 kHz, depending on the configuration.
The user should not consider these recommendations as a
substitute for using ADIsimCLK™ to determine the best loop
filter for a given application. ADIsimCLK is a free program that
can help with the design and exploration of the capabilities and
features of the AD9520, including the design of the PLL loop
filter. The Analog Devices website has a sample ADIsimCLK
file that includes the AD9520 default loop filter titled:
AD9520EvalBoardExample_148p5MHz.clk.
ADIsimCLK Version 1.3 includes specific support for the
AD9520. However, the AD9516, AD9520, and AD9522 share
the same loop dynamics. Therefore, ADIsimCLK Version 1.2
can also be used for modeling the AD9520 loop filter by selecting
the corresponding version of the AD9516. ADIsimCLK is available
at www.analog.com/clocks.
Table 2 shows the correspondence between the components
shown in Figure 27 and those on the evaluation board, as well
as the default values.
Table 2. AD9520 Evaluation Board Default Loop Filter Values
ADIsimCLK
Evaluation
Board Location
Clock Cleanup
(Default)
High
Loop BW
C1 C25 1500 pF 62 pF
R1 R5 2.1 kΩ 820 Ω
C2 C22 4.7 μF 240 nF
R2 R2 3 kΩ 390 Ω
C3 C31 2200 pF 33 pF