Datasheet

AD9520-0 Data Sheet
Rev. A | Page 78 of 80
LVPECL CLOCK DISTRIBUTION
The LVPECL outputs of the AD9520 provide the lowest jitter
clock signals available from the AD9520. The LVPECL outputs
(because they are open emitter) require a dc termination to bias
the output transistors. The simplified equivalent circuit in
Figure 54 shows the LVPECL output stage.
In most applications, an LVPECL far-end Thevenin termination
(see Figure 71) or Y-termination (see Figure 72) is recommended.
In both cases, V
S
of the receiving buffer should match V
S_DRV
. If it
does not, ac coupling is recommended (see Figure 73).
V
S_DRV
LVPECL
50Ω
50Ω
SINGLE-ENDED
(NOT COUPLED)
V
S
V
S_DRV
LVPECL
127Ω
127Ω
83Ω
83Ω
07213-045
Figure 71. DC-Coupled 3.3 V LVPECL Far-End Thevenin Termination
V
S_DRV
LVPECL
Z
0
= 50Ω
V
S
= V
S_DRV
LVPECL
50Ω
50Ω
50Ω
Z
0
= 50Ω
07213-047
Figure 72. DC-Coupled 3.3 V LVPECL Y-Termination
V
S_DRV
LVPECL
100Ω DIFFERENTIAL
(COUPLED)
TRANSMISSION LINE
V
S
LVPECL
100Ω
0.1nF
0.1nF
200Ω 200Ω
07213-046
Figure 73. AC-Coupled LVPECL with Parallel Transmission Line
LVPECL Y-Termination
LVPECL Y-termination is an elegant termination scheme that
uses the fewest components and offers both odd- and even-mode
impedance matching. Even-mode impedance matching is an
important consideration for closely coupled transmission lines
at high frequencies. Its main drawback is that it offers limited
flexibility for varying the drive strength of the emitter-follower
LVPECL driver. This can be an important consideration when
driving long trace lengths but is usually not an issue. In the case
where V
S_DRV
= 2.5 V, the 50 Ω termination resistor connected to
ground in Figure 72 should be changed to 19 Ω.
Far-End Thevenin Termination
Far-end Thevenin termination uses a resistor network to provide
50 Ω termination to a dc voltage that is below V
OL
of the LVPECL
driver. In this case, V
S_DRV
on the AD9520 should equal V
S
of the
receiving buffer. Although the resistor combination shown results
in a dc bias point of V
S_DRV
− 2 V, the actual common-mode voltage
is V
S_DRV
− 1.3 V because there is additional current flowing from
the AD9520 LVPECL driver through the pull-down resistor.
The circuit is identical for the case where V
S_DRV
= 2.5 V, except that
the pull-down resistor is 62.5 Ω and the pull-up resistor is 250 Ω.
CMOS CLOCK DISTRIBUTION
The output drivers of the AD9520 can be configured as CMOS
drivers. When selected as a CMOS driver, each output becomes
a pair of CMOS outputs, each of which can be individually turned
on or off and set as inverting or noninverting. These outputs are
3.3 V or 2.5 V CMOS compatible. However, every output driver
(including the LVPECL drivers) must be run at either 2.5 V or
3.3 V. The user cannot mix and match 2.5 V and 3.3 V outputs.
When using single-ended CMOS clocking, consider the following
guidelines:
• Using the CMOS drivers in the same output channel group
as the LVPECL drivers may result in performance degradation
of the LVPECL drivers. Where possible, program the two
CMOS drivers that form the same output of a differential
pair to be out of phase such that one driver is high while
the other is low. It is recommended that the evaluation
board be used to verify the performance of the AD9520 in
demanding applications where both CMOS and LVPECL
drivers are in the same group, and the very best jitter
performance is required.
• If possible, design point-to-point connections such that
each driver has only one receiver. Connecting outputs in
this manner allows for simple termination schemes and
minimizes ringing due to possible mismatched impedances
on the output trace. Series termination at the source is
generally required to provide transmission line matching
and/or to reduce current transients at the driver.
• The value of the resistor is dependent on the board design
and timing requirements (typically 10 Ω to 100 Ω is used).
CMOS outputs are also limited in terms of the capacitive
load or trace length that they can drive. Typically, trace
lengths of less than 3 inches are recommended to preserve
signal rise/fall times and signal integrity.
CMOS CMOS
10Ω
60.4Ω
(1.0 INCH)
MICROSTRIP
07213-076
Figure 74. Series Termination of CMOS Output