Datasheet

Data Sheet AD9520-0
Rev. A | Page 73 of 80
Reg.
Addr.
(Hex) Bits Name Description
0x195 [7:3] Unused Unused.
2 Channel 1 power-down Channel 1 powers down.
0: normal operation (default).
1: powered down. (Setting this bit puts OUT3/
OUT3
, OUT4/
OUT4
, and OUT5/
OUT5
into safe
power-down mode.)
1 Channel 1 direct to output Connects OUT3, OUT4, and OUT5 to Divider 1 or directly to VCO or CLK.
0: OUT3, OUT4, and OUT5 are connected to Divider 1 (default).
1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT3, OUT4, and OUT5.
If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT3, OUT4, and OUT5.
If Register 0x1E1[1:0] = 01b, there is no effect.
0 Disable Divider 1 DCC Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
0x196 [7:4] Divider 2 low cycles Number of clock cycles (minus 1) of the divider input during which the divider output stays low.
A value of 0x1 means that the divider is low for two input clock cycles (default: 0x1).
[3:0] Divider 2 high cycles Number of clock cycles (minus 1) of the divider input during which the divider output stays high.
A value of 0x1 means that the divider is high for two input clock cycles (default: 0x1).
0x197 7 Divider 2 bypass Bypasses and powers down the divider; routes input to divider output.
0: uses divider (default).
1: bypasses divider.
6 Divider 2 ignore SYNC Ignores SYNC.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
5
Divider 2 force high
Forces divider output to a specific state. This requires that ignore SYNC also be set. Note that
this bit has no effect if the channel divider is bypassed, but the driver polarity can still be reversed.
0: divider output is forced to low (default).
1: divider output is forced to the setting stored in Bit 4 of this register.
4 Divider 2 start high Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
[3:0] Divider 2 phase offset Phase offset (default: 0x0).
0x198
[7:3]
Unused
Unused.
2 Channel 2 power-down Channel 2 powers down.
0: normal operation (default).
1: powered down. (Setting this bit puts OUT6/
OUT6
, OUT7/
OUT7
, and OUT8/
OUT8
into safe
power-down mode.)
1 Channel 2 direct to output Connects OUT6, OUT7, and OUT8 to Divider 2 or directly to VCO or CLK.
0: OUT6, OUT7, and OUT8 are connected to Divider 2 (default).
1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT6, OUT7, and OUT8.
If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT6, OUT7, and OUT8.
If Register 0x1E1[1:0] = 01b, there is no effect.
0 Disable Divider 2 DCC Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
0x199 [7:4] Divider 3 low cycles Number of clock cycles (minus 1) of the divider input during which the divider output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default: 0x0).
[3:0] Divider 3 high cycles Number of clock cycles (minus 1) of the divider input during which the divider output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default: 0x0).