Datasheet

AD9520-0 Data Sheet
Rev. A | Page 48 of 80
1 2 3 4 5 6 7
8
9 10
INPUT TO VCO DIVIDER
INPUT TO CHANNEL DIVIDER
OUTPUT OF
CHANNEL DIVIDER
SYNC PIN
1
11
12
13 14
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT
CHANNEL DIVIDER OUTPUT STATIC
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER
OUTPUT CLOCKING
07213-073
Figure 52. SYNC Timing Pipeline Delay When the VCO Divider Is Used—CLK or VCO Is Input
INPUT TO CLK
INPUT TO CHANNEL DIVIDER
OUTPUT OF
CHANNEL DIVIDER
SYNC PIN
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT
1 2 3 4 5 6 7
8
9 10
11
12
13 14
1
CHANNEL DIVIDER OUTPUT STATIC
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER
OUTPUT CLOCKING
07213-074
Figure 53. SYNC Timing Pipeline Delay When the VCO Divider Is Not Used—CLK Input Only