Datasheet

Data Sheet AD9520-0
Rev. A | Page 37 of 80
Prescaler
The prescaler of the AD9520 allows for two modes of operation:
a fixed divide (FD) mode of 1, 2, or 3, and a dual modulus (DM)
mode where the prescaler divides by P and (P + 1) {2 and 3,
4 and 5, 8 and 9, 16 and 17, or 32 and 33}. The prescaler modes
of operation are given in Table 54, Register 0x016[2:0]. Not all
modes are available at all frequencies (see Table 2).
When operating the AD9520 in dual modulus mode, P/(P + 1),
the equation used to relate the input reference frequency to the
VCO output frequency is
f
VCO
= (f
REF
/R) × (P × B + A) = f
REF
× N/R
However, when operating the prescaler in FD Mode 1, FD Mode 2,
or FD Mode 3, the A counter is not used (A = 0; the divide is a
fixed divide of P = 2, 4, 8, 16, or 32) and the equation simplifies to
f
VCO
= (f
REF
/R) × (P × B) = f
REF
× N/R
By using combinations of DM and FD modes, the AD9520 can
achieve values of N from 1 to 262,175.
Table 29 shows how a 10 MHz reference input can be locked to
any integer multiple of N.
Note that the same value of N can be derived in different ways,
as illustrated by the case of N = 12. The user can choose a fixed
divide mode of P = 2 with B = 6; use the dual modulus mode of
2/3 with A = 0, B = 6; or use the dual modulus mode of 4/5 with
A = 0, B = 3.
A and B Counters
The B counter must be ≥3 or bypassed, and, unlike the R counter,
A = 0 is actually zero.
When the prescaler is in dual modulus mode, the A counter
must be equal to or less than the B counter.
The maximum input frequency to the A/B counter is reflected
in the maximum prescaler output frequency (~300 MHz) that is
specified in Table 2 This is the prescaler input frequency (VCO or
CLK) divided by P. For example, a dual modulus mode of P = 8/9
is not allowed if the VCO frequency is greater than 2400 MHz
because the frequency going to the A/B counter is too high.
When the AD9520 B counter is bypassed (B = 1), the A counter
should be set to zero, and the overall resulting divide is equal to
the prescaler setting, P. The possible divide ratios in this mode are
1, 2, 3, 4, 8, 16, and 32. This mode is useful only when an external
VCO/VCXO is used because the frequency range of the internal
VCO requires an overall feedback divider greater than 32.
Although manual reset is not normally required, the A/B counters
have their own reset bit. Alternatively, the A and B counters can be
reset using the shared reset bit of the R, A, and B counters. Note
that these reset bits are not self-clearing.
R, A, and B Counters—
SYNC
Pin Reset
The R, A, and B counters can be reset simultaneously through the
SYNC
pin. This function is controlled by Register 0x019[7:6] (see
Table 54). The
SYNC
pin reset is disabled by default.
R and N Divider Delays
Both the R and N dividers feature a programmable delay cell.
These delays can be enabled to allow adjustment of the phase
relationship between the PLL reference clock and the VCO or
CLK. Each delay is controlled by three bits. The total delay
range is about 1 ns. See Register 0x019 in Table 2 and Table 54.
Table 29. How a 10 MHz Reference Input Can Be Locked to Any Integer Multiple of N
f
REF
(MHz) R P A B N f
VCO
(MHz) Mode Description
10 1 1 X
1
1 1 10 FD P = 1, B = 1 (A and B counters are bypassed).
10 1 2 X
1
1 2 20 FD P = 2, B = 1 (A and B counters are bypassed).
10 1 1 X
1
3 3 30 FD A counter is bypassed.
10 1 1 X
1
4 4 40 FD A counter is bypassed.
10 1 1 X
1
5 5 50 FD A counter is bypassed.
10 1 2 X
1
3 6 60 FD A counter is bypassed.
10 1 2 0 3 6 60 DM
10 1 2 1 3 7 70 DM
Maximum frequency into prescaler in P = 2/3 mode is 200 MHz.
If N = 7 or N = 11 is desired for prescaler input frequency of 200 MHz
to 300 MHz, use P = 1 and N = 7 or 11, respectively.
10 1 2 2 3 8 80 DM
10 1 2 1 4 9 90 DM
10 1 8 6 18 150 1500 DM
10 1 8 7 18 151 1510 DM
10 1 16 7 9 151 1510 DM
10 10 32 6 47 1510 1510 DM
10 1 8 0 25 200 2000 DM
10 1 16 0 15 240 2400 DM
10 10 32 0 75 2400 2400 DM
1
X = don’t care