Datasheet

AD9520-0 Data Sheet

Rev. A | Page 32 of 80

Mode 2—High Frequency Clock Distribution; CLK or

External VCO > 1600 MHz

The AD9520 power-up default configuration has the PLL powered

off and the routing of the input set so that the CLK/

CLK

input

is connected to the distribution section through the VCO divider

(divide-by-1/divide-by-2/divide-by-3/divide-by-4/divide-by-5/

divide-by-6). This is a distribution only mode that allows for

an external input up to 2400 MHz (see Table 3). The maximum

frequency that can be applied to the channel dividers is 1600 MHz;

therefore, higher input frequencies must be divided down before

reaching the channel dividers.

When the PLL is enabled, this routing also allows the use of the

PLL with an external VCO or VCXO with a frequency of less than

2400 MHz. In this configuration, the internal VCO is not used and

is powered off. The external VCO/VCXO feeds directly into the

prescaler.

The register settings shown in Table 26 are the default values of

these registers at power-up or after a reset operation.

Table 26. Default Register Settings for Clock Distribution

Mode

0x010[1:0] = 01b PLL asynchronous power-down (PLL off)

0x1E0[2:0] = 000b Set VCO divider = 2

0x1E1[0] = 0b Use the VCO divider

0x1E1[1] = 0b Select CLK as the source

When the internal PLL is used with an external VCO, the PLL

must be turned on.

Table 27. Settings When Using an External VCO

0x010[1:0] = 00b PLL normal operation (PLL on)

0x010 to 0x01E PLL settings; select and enable a reference

input; set R, N (P, A, B), PFD polarity, and I

according to the intended loop

configuration

0x1E1[1] = 0b Select CLK as the source

An external VCO requires an external loop filter that must be

connected between CP and the tuning pin of the VCO. This

loop filter determines the loop bandwidth and stability of the

PLL. Make sure to select the proper PFD polarity for the VCO

being used.

Table 28. Setting the PFD Polarity

0x010[7] = 0b PFD polarity positive (higher control

voltage produces higher frequency)

0x010[7] = 1b PFD polarity negative (higher control

voltage produces lower frequency)