Datasheet

AD9518-4 Data Sheet
Rev. B | Page 58 of 64
Reg.
Addr
(Hex) Bits Name Description
0x1E1 4 Power down clock input section Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree).
0: normal operation (default).
1: power-down.
3 Power down VCO clock interface Powers down the interface block between VCO and clock distribution.
0: normal operation (default).
1: power-down.
2 Power down VCO and CLK Powers down both VCO and CLK input.
0; normal operation (default).
1: power-down.
1 Select VCO or CLK Selects either the VCO or the CLK as the input to VCO divider.
0: selects external CLK as input to VCO divider (default).
1: selects VCO as input to VCO divider; cannot bypass VCO divider when this is selected.
0 Bypass VCO divider Bypasses or uses the VCO divider.
0: uses VCO divider (default).
1: bypasses VCO divider; cannot select VCO as input when this is selected.
Table 48. System
Reg.
Addr.
(Hex) Bits Name Description
0x230 2 Power down SYNC Powers down the sync function.
0: normal operation of the sync function (default).
1: powers down sync circuitry.
1 Powers down the reference for distribution section.
Power down distribution
reference
0: normal operation of the reference for the distribution section (default).
1: powers down the reference for the distribution section.
0 Soft sync
The soft sync bit works the same as the SYNC
pin, except that the polarity of the bit
is reversed. That is, a high level forces selected channels into a predetermined static
state, and a 1-to-0 transition triggers a sync.
0: same as SYNC
high (default).
1: same as SYNC
low.
Table 49. Update All Registers
Reg.
Addr
(Hex) Bits Name Description
0x232 0 Update all registers
This bit must be set to 1b to transfer the contents of the buffer registers into the active
registers, which happens on the next SCLK rising edge. This bit is self-clearing; that is,
it does not have to be set back to 0b.
1 (self-clearing): updates all active registers to the contents of the buffer registers.