Datasheet

AD9518-4 Data Sheet
Rev. B | Page 46 of 64
Reg.
Addr.
(Hex)
Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
Default
Value
(Hex)
LVPECL Outputs
0x0F0 OUT0 Blank OUT0
invert
OUT0 LVPECL
differential voltage
OUT0 power-down 0x08
0x0F1 OUT1 Blank OUT1
invert
OUT1 LVPECL
differential voltage
OUT1 power-down 0x0A
0x0F2 OUT2 Blank OUT2
invert
OUT2 LVPECL
differential voltage
OUT2 power-down 0x08
0x0F3 OUT3 Blank OUT3
invert
OUT3 LVPECL
differential voltage
OUT3 power-down 0x0A
0x0F4 OUT4 Blank OUT4
invert
OUT4 LVPECL
differential voltage
OUT4 power-down 0x08
0x0F5 OUT5 Blank OUT5
invert
OUT5 LVPECL
differential voltage
OUT5 power-down 0x0A
0x0F6
to
0x13F
Blank
0x140
to
0x143
Reserved
0x144
to
0x18F
Blank
LVPECL Channel Dividers
0x190 Divider 0
(PECL)
Divider 0 low cycles Divider 0 high cycles 0x00
0x191 Divider 0
bypass
Divider 0
nosync
Divider 0
force high
Divider 0
start high
Divider 0 phase offset 0x80
0x192 Blank Reserved Divider 0
direct to
output
Divider 0
DCCOFF
0x00
0x193 Divider 1
(PECL)
Divider 1 low cycles Divider 1 high cycles 0xBB
0x194 Divider 1
bypass
Divider 1
nosync
Divider 1
force high
Divider 1
start high
Divider 1 phase offset 0x00
0x195 Blank Reserved Divider 1
direct to
output
Divider 1
DCCOFF
0x00
0x196 Divider 2
(PECL)
Divider 2 low cycles Divider 2 high cycles 0x00
0x197 Divider 2
bypass
Divider 2
nosync
Divider 2
force high
Divider 2
start high
Divider 2 phase offset 0x00
0x198 Blank Reserved Divider 2
direct to
output
Divider 2
DCCOFF
0x00
0x199
to
0x1A3
Reserved
0x1A4
to
0x1DF
Blank
VCO Divider and CLK Input
0x1E0 VCO divider Blank Reserved VCO Divider 0x02
0x1E1 Input CLKs Reserved Power
down
clock input
section
Power down
VCO clock
interface
Power
down VCO
and CLK
Select
VCO or CLK
Bypass VCO
divider
0x00
0x1E2
to
0x22A
Blank