Datasheet

AD9518-1 Data Sheet
Rev. C | Page 12 of 64
TIMING DIAGRAMS
CL
K
t
CLK
t
PECL
06430-060
Figure 2. CLK/
CLK
to Clock Output Timing, DIV = 1
DIFFERENTIAL
LVPECL
80%
20%
t
RP
t
FP
06430-061
Figure 3. LVPECL Timing, Differential