FUNCTIONAL BLOCK DIAGRAM CP REF1 REFIN REF2 CLK LF STATUS MONITOR PLL Low phase noise, phase-locked loop (PLL) On-chip VCO tunes from 2.30 GHz to 2.65 GHz External VCO/VCXO to 2.4 GHz optional 1 differential or 2 single-ended reference inputs Reference monitoring capability Automatic revertive and manual reference switchover/holdover modes Accepts LVPECL, LVDS, or CMOS references to 250 MHz Programmable delays in path to PFD Digital or analog lock detect, selectable 3 pairs of 1.
AD9518-1 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Resistance .................................................................... 13 Applications ....................................................................................... 1 ESD Caution................................................................................ 13 General Description .....................................................
Data Sheet AD9518-1 REVISION HISTORY 1/12—Rev. B to Rev. C Change to 0x232 Description, Table 49........................................58 9/11—Rev. A to Rev. B Changes to Applications and General Description Sections ....... 1 Change to CPRSET Pin Resistor Parameter, Table 1 .................... 4 Changes to Table 2 ............................................................................ 4 Change to Test Conditions/Comments Column of Output Differential Voltage (VOD) Parameter, Table 4 ..............
AD9518-1 Data Sheet SPECIFICATIONS Typical values are given for VS = VS_LVPECL = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ, unless otherwise noted. Minimum and maximum values are given over full VS and TA (−40°C to +85°C) variation. POWER SUPPLY REQUIREMENTS Table 1. Parameter VS VS_LVPECL VCP RSET Pin Resistor CPRSET Pin Resistor Min 3.135 2.375 VS 2.7 BYPASS Pin Capacitor Typ 3.3 4.12 5.1 Max 3.465 VS 5.25 10 220 Unit V V V kΩ kΩ nF Test Conditions/Comments 3.
Data Sheet Parameter CHARGE PUMP (CP) ICP Sink/Source High Value Low Value Absolute Accuracy CPRSET Range ICP High Impedance Mode Leakage Sink-and-Source Current Matching ICP vs. CPV ICP vs.
AD9518-1 Data Sheet CLOCK INPUTS Table 3. Parameter CLOCK INPUTS (CLK, CLK) Input Frequency Min Typ 01 01 Input Sensitivity, Differential 1 Unit 2.4 1.6 GHz GHz mV p-p 2 V p-p 1.8 1.8 V V mV p-p kΩ pF 150 Input Level, Differential Input Common-Mode Voltage, VCM Input Common-Mode Range, VCMR Input Sensitivity, Single-Ended Input Resistance Input Capacitance Max 1.3 1.3 3.9 1.57 150 4.7 2 5.
Data Sheet AD9518-1 CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED) Table 6.
AD9518-1 Data Sheet CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO) Table 8. Parameter LVPECL OUTPUT ABSOLUTE TIME JITTER Min VCO = 2.46 GHz; LVPECL = 491.52 MHz; PLL LBW = 55 kHz Typ Max 142 370 145 356 195 402 VCO = 2.46 GHz; LVPECL = 122.88 MHz; PLL LBW = 55 kHz VCO = 2.46 GHz; LVPECL = 61.
Data Sheet AD9518-1 CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED) Table 11. Parameter LVPECL OUTPUT ADDITIVE TIME JITTER Min Typ Max Unit CLK = 622.08 MHz; LVPECL = 622.08 MHz; Divider = 1 CLK = 622.08 MHz; LVPECL = 155.52 MHz; Divider = 4 CLK = 1.
AD9518-1 Data Sheet SERIAL CONTROL PORT Table 13.
Data Sheet AD9518-1 LD, STATUS, AND REFMON PINS Table 15. Parameter OUTPUT CHARACTERISTICS Min Output Voltage High (VOH) Output Voltage Low (VOL) MAXIMUM TOGGLE RATE 2.7 Max Unit 0.4 100 V V MHz 3 pF On-chip capacitance; used to calculate RC time constant for analog lock detect readback; use a pull-up resistor 1.
AD9518-1 Data Sheet TIMING DIAGRAMS DIFFERENTIAL tCLK 80% CLK 20% tRP tFP Figure 3. LVPECL Timing, Differential Figure 2. CLK/CLK to Clock Output Timing, DIV = 1 Rev.
Data Sheet AD9518-1 ABSOLUTE MAXIMUM RATINGS Table 17. Parameter VS, VS_LVPECL to GND VCP to GND REFIN, REFIN to GND REFIN to REFIN RSET to GND CPRSET to GND CLK, CLK to GND CLK to CLK SCLK, SDIO, SDO, CS to GND OUT0, OUT0, OUT1, OUT1, OUT2, OUT2, OUT3, OUT3,OUT4, OUT4, OUT5, OUT5 to GND SYNC to GND REFMON, STATUS, LD to GND Junction Temperature 1 Storage Temperature Range Lead Temperature (10 sec) 1 Rating −0.3 V to +3.6 V −0.3 V to +5.8 V −0.3 V to VS + 0.3 V −3.3 V to +3.3 V −0.3 V to VS + 0.3 V −0.
AD9518-1 Data Sheet 1 37 VS 38 OUT1 39 OUT1 40 VS_LVPECL 41 OUT0 42 OUT0 44 RSET 45 VS 46 CPRSET 43 VS 36 PIN 1 INDICATOR 2 35 3 34 4 33 5 32 6 AD9518-1 31 7 TOP VIEW (Not to Scale) 30 8 NC VS GND OUT2 OUT2 VS_LVPECL VS_LVPECL 29 OUT3 OUT3 27 GND 26 VS 25 VS 28 9 10 11 06430-003 24 23 22 21 20 19 18 17 16 15 SCLK CS SDO SDIO RESET PD OUT4 OUT4 VS_LVPECL OUT5 OUT5 VS 14 12 13 REFMON LD VCP CP STATUS REF_SEL SYNC LF BYPASS VS CLK CLK 47 REFIN (REF2) 48 REFIN
Data Sheet AD9518-1 Input/ Output I I Pin Type 3.3 V CMOS 3.3 V CMOS Mnemonic SCLK CS 15 16 17 18 19 20 21, 30, 31, 40 22 23 27, 34 28 29 32 33 36 38 39 41 42 44 O I/O I I O O I 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS LVPECL LVPECL Power SDO SDIO RESET PD OUT4 OUT4 VS_LVPECL Description Serial Control Port Data Clock Signal. Serial Control Port Chip Select, Active Low. This pin has an internal 30 kΩ pull-up resistor. Serial Control Port. Unidirectional serial data output. Serial Control Port.
AD9518-1 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 300 5.0 3 CHANNELS—6 LVPECL 280 4.5 220 3 CHANNELS—3 LVPECL 180 160 2 CHANNELS—2 LVPECL 140 3.5 PUMP DOWN 2.5 2.0 1.5 1.0 120 500 1000 1500 2000 2500 3000 FREQUENCY (MHz) 0 06430-007 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOLTAGE ON CP PIN (V) Figure 5. Current vs. Frequency, Direct to Output, LVPECL Outputs 06430-012 0.5 1 CHANNEL—1 LVPECL 100 Figure 8. Charge Pump Characteristics at VCP = 5.
Data Sheet AD9518-1 1.0 1.9 DIFFERENTIAL OUTPUT (V) VCO TUNING VOLTAGE (V) 1.8 1.7 1.6 1.5 1.4 0.6 0.2 –0.2 –0.6 2.4 2.5 2.6 2.7 FREQUENCY (GHz) –1.0 06430-138 1.2 2.3 0 5 10 15 20 25 TIME (ns) Figure 11. VCO Tuning Voltage vs. Frequency (Note that VCO calibration centers the dc tuning voltage for the PLL setup that is active during calibration.) 06430-014 1.3 Figure 14. LVPECL Output (Differential) at 100 MHz 10 1.
Data Sheet –70 –120 –80 –125 –90 –130 PHASE NOISE (dBc/Hz) –100 –110 –120 –130 –140 –140 –145 –150 –155 100k 1M 10M 100M FREQUENCY (Hz) –160 10 06430-023 –150 10k –135 Figure 17. Internal VCO Phase Noise (Absolute) Direct to LVPECL at 2650 MHz 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) 06430-026 PHASE NOISE (dBc/Hz) AD9518-1 Figure 20. Phase Noise (Additive) LVPECL at 245.
AD9518-1 –120 –130 –130 –140 –150 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 23. Phase Noise (Absolute) Clock Generation; Internal VCO at 2.4576 GHz; PFD = 15.36 MHz; LBW = 55 kHz; LVPECL Output = 122.88 MHz –150 –160 1k 10k 100k 100M 1000 OC-48 OBJECTIVE MASK AD9518 INPUT JITTER AMPLITUDE (UI p-p) –80 –90 PHASE NOISE (dBc/Hz) 10M Figure 25. Phase Noise (Absolute); External VCXO (Toyocom TCO-2112) at 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.
AD9518-1 Data Sheet TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0° to 360° for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as being Gaussian (normal) in distribution.
Data Sheet AD9518-1 DETAILED BLOCK DIAGRAM REF_ SEL VS GND RSET REFMON DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD REF1 STATUS R DIVIDER STATUS REFIN (REF1) PLL REFERENCE LOCK DETECT REF2 PROGRAMMABLE R DELAY VCO STATUS REFIN (REF2) BYPASS CPRSET VCP LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR HOLD CHARGE PUMP CP N DIVIDER LF VCO STATUS DIVIDE BY 2, 3, 4, 5, OR 6 CLK CLK 1 OUT0 DIVIDE BY 1 TO 32 PD SYNC 0 OUT0
AD9518-1 Data Sheet THEORY OF OPERATION OPERATIONAL CONFIGURATIONS Table 20. Default Settings of Some PLL Registers The AD9518 can be configured in several ways. These configurations must be set up by loading the control registers (see Table 42 and Table 43 through Table 49). Each section or function must be individually programmed by setting the appropriate bits in the corresponding control register or registers.
Data Sheet AD9518-1 REF_ SEL VS GND RSET REFMON DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD REF1 STATUS R DIVIDER STATUS REFIN (REF1) PLL REFERENCE LOCK DETECT REF2 PROGRAMMABLE R DELAY VCO STATUS REFIN (REF2) BYPASS CPRSET VCP LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR HOLD CHARGE PUMP CP N DIVIDER LF VCO STATUS DIVIDE BY 2, 3, 4, 5, OR 6 CLK CLK 1 OUT0 DIVIDE BY 1 TO 32 PD SYNC 0 OUT0 LVPECL OUT1 DIGITAL LO
AD9518-1 Data Sheet Internal VCO and Clock Distribution Table 23. Settings When Using an Internal VCO When using the internal VCO and PLL, the VCO divider must be employed to ensure that the frequency presented to the channel dividers does not exceed their specified maximum frequency of 1600 MHz (see Table 3). The internal PLL uses an external loop filter to set the loop bandwidth. The external loop filter is also crucial to the loop stability.
Data Sheet AD9518-1 REF_ SEL VS GND RSET REFMON DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD REF1 STATUS R DIVIDER STATUS REFIN (REF1) PLL REFERENCE LOCK DETECT REF2 PROGRAMMABLE R DELAY VCO STATUS REFIN (REF2) BYPASS CPRSET VCP LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR HOLD CHARGE PUMP CP N DIVIDER LF VCO STATUS DIVIDE BY 2, 3, 4, 5, OR 6 CLK CLK 1 0 OUT0 DIVIDE BY 1 TO 32 PD SYNC OUT0 LVPECL OUT1 DIGITAL LO
AD9518-1 Data Sheet Phase-Locked Loop (PLL) REF_SEL VS GND RSET REFMON CPRSET VCP DIST REF REFERENCE SWITCHOVER LD LOCK DETECT REF1 STATUS REF2 PROGRAMMABLE R DELAY R DIVIDER STATUS PLL REF HOLD REFIN (REF1) REFIN (REF2) BYPASS N DIVIDER LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP VCO STATUS LF STATUS DIVIDE BY 2, 3, 4, 5, OR 6 CLK 0 1 CLK 1 06430-064 VCO 0 Figure 31.
Data Sheet AD9518-1 Charge Pump (CP) AD9518-1 VCO LF 31pF R2 CP R1 CHARGE PUMP BYPASS C1 C2 C3 06430-065 The charge pump is controlled by the PFD. The PFD monitors the phase and frequency relationship between its two inputs, and tells the CP to pump up or pump down to charge or discharge the integrating node (part of the loop filter).
AD9518-1 Data Sheet In differential mode, the reference input pins are internally selfbiased so that they can be ac-coupled via capacitors. It is possible to dc couple to these inputs. If the differential REFIN is driven by a single-ended signal, the unused side (REFIN) should be decoupled via a suitable capacitor to a quiet ground. Figure 34 shows the equivalent circuit of REFIN. VS Automatic revertive switchover relies on the REFMON pin to indicate when REF1 disappears.
Data Sheet AD9518-1 By using combinations of the DM and FD modes, the AD9518 can achieve values of N all the way down to N = 1 and up to N = 262,175. Table 27 shows how a 10 MHz reference input can be locked to any integer multiple of N. Note that the same value of N can be derived in different ways, as illustrated by the case of N = 12. The user can choose a fixed divide mode of P = 2 with B = 6, use the dual modulus mode of 2/3 with A = 0, B = 6, or use the dual modulus mode of 4/5 with A = 0, B = 3.
AD9518-1 Data Sheet By selecting the proper output through the mux on each pin, the DLD function can be made available at the LD, STATUS, and REFMON pins. The DLD circuit indicates a lock when the time difference of the rising edges at the PFD inputs is less than a specified value (the lock threshold). The loss of a lock is indicated when the time difference exceeds a specified value (the unlock threshold).
Data Sheet AD9518-1 Holdover Automatic/Internal Holdover Mode The AD9518 PLL has a holdover function, which is implemented by putting the charge pump into a state of high impedance. This is useful when the PLL reference clock is lost. Holdover mode allows the VCO to maintain a relatively constant frequency even though there is no reference clock. Without this function, the charge pump is placed into a constant pump-up or pumpdown state, resulting in a massive VCO frequency shift.
AD9518-1 Data Sheet The holdover function senses the logic level of the LD pin as a condition to enter holdover. The signal at LD can be from the DLD, ALD, or current source LD mode. It is possible to disable the LD comparator (Register 0x01D[3]), which causes the holdover function to always sense LD as high. If DLD is used, it is possible for the DLD signal to chatter some while the PLL is reacquiring lock. The holdover function may retrigger, thereby preventing the holdover mode from ever terminating.
Data Sheet AD9518-1 REF_SEL VS GND RSET REFMON DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD REF1 LOCK DETECT STATUS R DIVIDER STATUS REFIN (REF1) PLL REFERENCE REF2 CPRSET VCP PROGRAMMABLE R DELAY REFIN (REF2) BYPASS LOW DROPOUT REGULATOR (LDO) N DIVIDER P, P + 1 PRESCALER A/B COUNTERS LF PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR HOLD CHARGE PUMP CP VCO STATUS VCO STATUS 0 DIVIDE BY 2, 3, 4, 5, OR 6 CLK 1 1 06430-070 CLK 0 Figure 39.
AD9518-1 Data Sheet Table 28. Example Time to Complete a VCO Calibration with Different fREFIN Frequencies fREFIN (MHz) 100 10 10 R Divider 1 10 100 PFD 100 MHz 1 MHz 100 kHz Time to Calibrate VCO 88 µs 8.8 ms 88 ms VCO calibration must be manually initiated. This allows for flexibility in deciding what order to program registers and when to initiate a calibration, instead of having it happen every time certain PLL registers have their values change.
Data Sheet AD9518-1 Either the internal VCO or the CLK can be selected as the source for the direct-to-output routing. Table 30.
AD9518-1 Data Sheet Table 33. Duty Cycle with VCO Divider, Input Duty Cycle Is 50% Even, Odd DX N+M+2 1 (divider bypassed) 1 (divider bypassed) 1 (divider bypassed) Even Even, Odd Odd VCO Divider Even Odd = 3 Odd = 5 Output Duty Cycle DCCOFF = 1 DCCOFF = 0 50% 50% 33.3% 50% 40% 50% (N + 1)/ (N + M + 2) (N + 1)/ (N + M + 2) 50%; requires M = N 50%; requires M = N + 1 Table 34.
Data Sheet AD9518-1 Synchronizing the Outputs—Sync Function The most common way to execute the sync function is to use the SYNC pin to do a manual synchronization of the outputs. This requires a low-going signal on the SYNC pin, which is held low and then released when synchronization is desired. The timing of the sync operation is shown in Figure 41 (using the VCO divider) and Figure 42 (VCO divider not used).
AD9518-1 Data Sheet A sync operation brings all outputs that have not been excluded (by the nosync bit) to a preset condition before allowing the outputs to begin clocking in synchronicity. The preset condition takes into account the settings in each of the channel’s start high bit and its phase offset.
Data Sheet AD9518-1 If the AD9518 clock outputs must be synchronized to each other, a sync is required upon exiting power-down (see the Synchronizing the Outputs—Sync Function section). A VCO calibration is not required when exiting power-down. PLL Power-Down The PLL section of the AD9518 can be selectively powered down. There are three PLL operating modes set by Register 0x010[1:0], as shown in Table 44. In asynchronous power-down mode, the device powers down as soon as the registers are updated.
AD9518-1 Data Sheet SERIAL CONTROL PORT The AD9518 serial control port is a flexible, synchronous, serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. The AD9518 serial control port is compatible with most synchronous transfer formats, including both the Motorola SPI and Intel® SSR® protocols. The serial control port allows read/write access to all registers that configure the AD9518.
Data Sheet AD9518-1 Read If the instruction word is for a read operation, the next N × 8 SCLK cycles clock out the data from the address specified in the instruction word, where N is 1 to 3 as determined by [W1:W0]. If N = 4, the read operation is in streaming mode, continuing until CS is raised. Streaming mode does not skip over reserved or blank registers. The readback data is valid on the falling edge of SCLK. The default mode of the AD9518 serial control port is the bidirectional mode.
AD9518-1 Data Sheet Table 39. Serial Control Port, 16-Bit Instruction Word, MSB First MSB I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 LSB I0 R/W W1 W0 A12 = 0 A11 = 0 A10 = 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CS SCLK DON'T CARE SDIO DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 16-BIT INSTRUCTION HEADER D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 REGISTER (N) DATA D4 D3 D2 D1 D0 DON'T CARE REGISTER (N – 1) DATA 06430-038 DON'T CARE Figure 46.
Data Sheet AD9518-1 tC tS CS tCLK tHIGH SCLK tLOW tDS SDIO BIT N BIT N + 1 Figure 51. Serial Control Port Timing Diagram—Write Table 40.
AD9518-1 Data Sheet THERMAL PERFORMANCE Table 41. Thermal Parameters for the 48-Lead LFCSP Symbol θJA θJMA θJMA θJB ΨJB ΨJB ΨJB θJC ΨJT ΨJT ΨJT Thermal Characteristic Using a JEDEC JESD51-7 Plus JEDEC JESD51-5 2S2P Test Board Junction-to-ambient thermal resistance, natural convection per JEDEC JESD51-2 (still air) Junction-to-ambient thermal resistance, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air) Junction-to-ambient thermal resistance, 2.
Data Sheet AD9518-1 CONTROL REGISTERS CONTROL REGISTER MAP OVERVIEW Table 42. Control Register Map Overview Reg. Addr.
AD9518-1 Reg. Addr.
Data Sheet Reg. Addr. (Hex) Parameter System Power-down 0x230 and sync AD9518-1 Bit 7 (MSB) 0x231 Update All Registers Update all 0x232 registers Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Power down sync Power down distribution reference Reserved Reserved Blank Blank Bit 0 (LSB) Default Value (Hex) Soft sync 0x00 0x00 Update all registers (self-clearing bit) 0x00 CONTROL REGISTER MAP DESCRIPTIONS Table 43 through Table 49 provide a detailed description of each of the control register functions.
AD9518-1 Data Sheet Table 44. PLL Reg. Addr.
Data Sheet Reg. Addr. (Hex) 0x017 Bits [2:0] [7:2] Name Prescaler P STATUS pin control AD9518-1 Description Prescaler: DM = dual modulus and FD = fixed divide. 2 1 0 Mode Prescaler 0 0 0 FD Divide-by-1. 0 0 1 FD Divide-by-2. 0 1 0 DM Divide-by-2 (2/3 mode). 0 1 1 DM Divide-by-4 (4/5 mode). 1 0 0 DM Divide-by-8 (8/9 mode). 1 0 1 DM Divide-by-16 (16/17 mode). 1 1 0 DM Divide-by-32 (32/33 mode) (default). 1 1 1 FD Divide-by-3. Selects the signal that is connected to the STATUS pin.
AD9518-1 Reg. Addr. (Hex) 0x018 0x019 Data Sheet Bits [1:0] Name Antibacklash pulse width [6:5] Lock detect counter 4 Digital lock detect window 3 Disable digital lock detect [2:1] VCO cal divider 0 VCO cal now [7:6] R, A, B counters, SYNC pin reset [5:3] [2:0] R path delay N path delay Description 1 0 Antibacklash Pulse Width (ns) 0 0 2.9 (default); this is the recommended setting, and it does not normally need to be changed. 0 1 1.
Data Sheet Reg. Addr. (Hex) 0x01A Bits 6 Name Reference frequency monitor threshold [5:0] LD pin control AD9518-1 Description Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect the VCO frequency monitor’s detection threshold (see Table 15: REF1, REF2, and VCO frequency status monitor). 0: frequency valid if frequency is above the higher frequency threshold (default). 1: frequency valid if frequency is above the lower frequency threshold.
AD9518-1 Reg. Addr. (Hex) 0x01B Data Sheet Bits 7 Name VCO frequency monitor 6 REF2 (REFIN) frequency monitor 5 REF1 (REFIN) frequency monitor [4:0] REFMON pin control Description Enables or disables VCO frequency monitor. 0: disables VCO frequency monitor (default). 1: enables VCO frequency monitor. Enables or disables REF2 frequency monitor. 0: disables REF2 frequency monitor (default). 1: enables REF2 frequency monitor.
Data Sheet Reg. Addr.
AD9518-1 Reg. Addr. (Hex) Data Sheet Bits 1 Name REF1 frequency > threshold 0 Digital lock detect Description Read-only register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency set by Register 0x01A, Bit 6. 0: REF1 frequency is less than threshold frequency. 1: REF1 frequency is greater than threshold frequency. Read-only register. Digital lock detect. 0: PLL is not locked. 1: PLL is locked. Table 45. LVPECL Outputs Reg. Addr.
Data Sheet Reg. Addr. (Hex) 0x0F3 0x0F4 0x0F5 Bits 4 Name OUT3 invert [3:2] OUT3 LVPECL differential voltage [1:0] OUT3 power-down 4 OUT4 invert [3:2] OUT4 LVPECL differential voltage [1:0] OUT4 power-down 4 OUT5 invert [3:2] OUT5 LVPECL differential voltage [1:0] OUT5 power-down AD9518-1 Description Sets the output polarity. 0: noninverting (default). 1: inverting. Sets the LVPECL output differential voltage (VOD). 3 2 VOD (mV) 0 0 400. 0 1 600. 1 0 780 (default). 1 1 960.
AD9518-1 Data Sheet Table 46. LVPECL Channel Dividers Reg. Addr.
Data Sheet Reg. Addr. (Hex) 0x195 0x196 0x197 0x198 Bits 1 Name Divider 1 direct to output 0 Divider 1 DCCOFF [7:4] Divider 2 low cycles [3:0] Divider 2 high cycles 7 Divider 2 bypass 6 Divider 2 nosync 5 Divider 2 force high 4 Divider 2 start high [3:0] 1 Divider 2 phase offset Divider 2 direct to output 0 Divider 2 DCCOFF AD9518-1 Description Connects OUT2 and OUT3 to Divider 1 or directly to VCO or CLK. 0: OUT2 and OUT3 are connected to Divider 1 (default).
AD9518-1 Reg. Addr (Hex) 0x1E1 Data Sheet Bits 4 Name Power down clock input section 3 Power down VCO clock interface 2 Power down VCO and CLK 1 Select VCO or CLK 0 Bypass VCO divider Description Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree). 0: normal operation (default). 1: power-down. Powers down the interface block between VCO and clock distribution. 0: normal operation (default). 1: power-down. Powers down both VCO and CLK input.
Data Sheet AD9518-1 APPLICATIONS INFORMATION Within the AD9518 family, lower VCO frequencies generally result in slightly lower jitter. The difference in integrated jitter (from 12 kHz to 20 MHz offset) for the same output frequency is usually less than 150 fs over the entire VCO frequency range (1.45 GHz to 2.95 GHz) of the AD9518 family.
AD9518-1 Data Sheet LVPECL CLOCK DISTRIBUTION VS_LVPECL In most applications, an LVPECL far-end Thevenin termination (see Figure 53) or Y-termination (see Figure 54) is recommended. In each case, the VS of the receiving buffer should match the VS_LVPECL voltage. If it does not, ac coupling is recommended (see Figure 55). In the case of Figure 55, pull-down resistors of <150 Ω are not recommended when VS_LVPECL = 3.3 V; if used, damage to the LVPECL drivers may result.
Data Sheet AD9518-1 OUTLINE DIMENSIONS 0.30 0.23 0.18 0.60 MAX 0.60 MAX 37 36 PIN 1 INDICATOR 6.85 6.75 SQ 6.65 48 0.50 REF (BOTTOM VIEW) 1.00 0.85 0.80 12° MAX 0.80 MAX 0.65 TYP 0.50 0.40 0.30 13 12 0.22 MIN 5.50 REF 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PIN 1 INDICATOR *5.55 5.50 SQ 5.45 EXPOSED PAD 25 24 TOP VIEW 1 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
AD9518-1 Data Sheet NOTES Rev.
Data Sheet AD9518-1 NOTES Rev.
AD9518-1 Data Sheet NOTES ©2007–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06430-0-1/12(C) Rev.
