Datasheet

AD9517-1 Data Sheet
Rev. E | Page 58 of 80
Reg.
Addr
(Hex) Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
Default
Value
(Hex)
LVPECL Channel Dividers
0x190 Divider 0
(PECL)
Divider 0 low cycles Divider 0 high cycles 0x00
0x191 Divider 0
bypass
Divider 0
nosync
Divider 0
force high
Divider 0
start high
Divider 0 phase offset 0x80
0x192 Blank Reserved Divider 0
direct to
output
Divider 0
DCCOFF
0x00
0x193
to
0x195
Reserved
0x196 Divider1
(PECL)
Divider 1 low cycles Divider 1 high cycles 0x00
0x197 Divider 1
bypass
Divider 1
nosync
Divider 1
force high
Divider 1
start high
Divider 1 phase offset 0x00
0x198 Blank Reserved Divider 1
direct to
output
Divider 1
DCCOFF
0x00
LVDS/CMOS Channel Dividers
0x199 Divider 2
(LVDS/CMOS)
Low Cycles Divider 2.1 High Cycles Divider 2.1 0x22
0x19A Phase Offset Divider 2.2 Phase Offset Divider 2.1 0x00
0x19B Low Cycles Divider 2.2 High Cycles Divider 2.2 0x11
0x19C Reserved Bypass
Divider 2.2
Bypass
Divider 2.1
Divider 2
nosync
Divider 2
force high
Start High
Divider 2.2
Start High
Divider 2.1
0x00
0x19D Blank Reserved Divider 2
DCCOFF
0x00
0x19E Divider 3
(LVDS/CMOS)
Low Cycles Divider 3.1 High Cycles Divider 3.1 0x22
0x19F Phase Offset Divider 3.2 Phase Offset Divider 3.1 0x00
0x1A0 Low Cycles Divider 3.2 High Cycles Divider 3.2 0x11
0x1A1 Reserved Bypass
Divider 3.2
Bypass
Divider 3.1
Divider 3
nosync
Divider 3
force high
Start High
Divider 3.2
Start High
Divider 3.1
0x00
0x1A2 Blank Reserved Divider 3
DCCOFF
0x00
0x1A3 Reserved
0x1A4
to
0x1DF
Blank
VCO Divider and CLK Input
0x1E0 VCO divider Blank Reserved VCO Divider 0x02
0x1E1 Input CLKs Reserved Power
down
clock input
section
Power down
VCO clock
interface
Power
down VCO
and CLK
Select
VCO or CLK
Bypass VCO
divider
0x00
0x1E2
to
0x22A
Blank
System
0x230 Power-down
and sync
Reserved Power
down sync
Power
down
distribution
reference
Soft sync 0x00
0x231 Blank Reserved 0x00
Update All Registers
0x232 Update all
registers
Blank Update all
registers (self-
clearing bit)
0x00