Datasheet

Data Sheet AD9517-1
Rev. E | Page 31 of 80
PROGRAMMABLE
N DELAY
REFIN (REF1)
REFIN (REF2)
CLK
CLK
REF1
REF2
AD9517-1
STATUS
STATUS
R
DIVIDER
VCO STATUS
PROGRAMMABLE
R DELAY
REFERENCE
SWITCHOVER
REF_ SEL CPRSET
V
CP
V
S GND RSET
DISTRIBUTION
REFERENCE
REFMON
CP
STATUS
LD
P, P + 1
PRESCALER
A/B
COUNTERS
N DIVIDER
BYPASS
LF
LOW DROPOUT
REGULATOR (LDO)
VCO
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
CHARGE
PUMP
PLL
REFERENCE
HOLD
OUT0
OUT1
OUT0
OUT1
LVPECL
DIVIDE BY
1 TO 32
OUT2
OUT3
OUT2
OUT3
LVPECL
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
LVDS/CMOS
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
LVDS/CMOS
DIVIDE BY
1 TO 32
01
PD
SYNC
RESET
SCLK
SDIO
SDO
CS
DIGITAL
LOGIC
SERIAL
CONTROL
PORT
OUT4 (OUT4A)
OUT4 (OUT4B)
OUT5 (OUT5A)
OUT5 (OUT5B)
OUT6 (OUT6A)
OUT6 (OUT6B)
OUT7 (OUT7A)
OUT7 (OUT7B)
DIVIDE BY
2, 3, 4, 5, OR 6
∆T
∆T
∆T
∆T
06425-028
Figure 45. Clock Distribution or External VCO < 1600 MHz