Datasheet

Data Sheet AD9517-1
Rev. E | Page 25 of 80
–100
–110
–120
–130
–140
–150
–160
10 100M10M1M100k10k1k100
PHASE NOISE (dBc/Hz)
FREQUENCY (Hz)
06425-132
Figure 37. Phase Noise (Additive) CMOS at 250 MHz, Divide-by-4
–120
–160
–150
–140
–130
1k 100M10M1M100k10k
PHASE NOISE (dBc/Hz)
FREQUENCY (Hz)
06425-141
Figure 38. Phase Noise (Absolute) Clock Generation; Internal VCO at
2.4576 GHz; PFD = 15.36 MHz; LBW = 55 kHz; LVPECL Output = 122.88 MHz
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
1k 100M10M1M100k10k
PHASE NOISE (dBc/Hz)
FREQUENCY (Hz)
06425-139
Figure 39. Phase Noise (Absolute) Clock Cleanup; Internal VCO at 2.488 GHz;
PFD = 19.44 MHz; LBW = 12.8 kHz; LVPECL Output = 155.52 MHz
–120
–160
–150
–140
–130
1k 100M10M1M100k10k
PHASE NOISE (dBc/Hz)
FREQUENCY (Hz)
06425-140
Figure 40. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112) at
245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz
1000
100
10
1
0.1
0.01 0.1 1 10 100 1000
INPUT JITTER AMPLITUDE (UI p-p)
JITTER FREQUENCY (kHz)
06425-148
OC-48 OBJECTIVE MASK
AD9517
NOTE: 375UI MAX AT 10Hz OFFSET IS THE
MAXIMUM JITTER THAT CAN BE
GENERATED BY THE TEST EQUIPMENT.
FAILURE POINT IS GREATER THAN 375UI.
f
OBJ
Figure 41. GR-253 Jitter Tolerance Plot