Datasheet
Data Sheet AD9516-3
Rev. C | Page 17 of 80
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CS
NC
NC
NC
SDO
SDIO
RESET
PD
OUT4
OUT4
VS_LVPECL
OUT5
OUT5
VS
VS
VS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
REFIN (REF1)
REFIN (REF2)
CPRSET
VS
VS
GND
RSET
VS
OUT0
OUT0
VS_LVPECL
OUT1
OUT1
VS
VS
VS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VS
REFMON
LD
VCP
CP
STATUS
REF_SEL
SYNC
LF
BYPASS
VS
VS
CLK
CLK
NC
SCLK
NC = NO CONNECT
OUT6 (OUT6A)
OUT6 (OUT6B)
OUT7 (OUT7A)
OUT7 (OUT7B)
GND
OUT2
OUT2
VS_LVPECL
OUT3
OUT3
VS
GND
OUT9 (OUT9B)
OUT9 (OUT9A)
OUT8 (OUT8B)
OUT8 (OUT8A)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD9516-3
TOP VIEW
(Not to Scale)
LVPECL LVPECL
LVPECL
LVPECL
LVPECL LVPECL
LVDS/CMOS
w/FINE DELAY ADJUST
LVDS/CMOS
w/FINE DELAY ADJUST
06422-003
NOTES
1. THE EXTERNAL PADDLE ON THE BOTTOM OF THE PACKAGE MUST BE
CONNECTED TO GROUND FOR PROPER OPERATION.
2. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
Figure 6. Pin Configuration
Table 20. Pin Function Descriptions
Pin No.
Input/
Output Pin Type Mnemonic Description
1, 11, 12, 30,
31, 32, 38,
49, 50, 51,
57, 60, 61
I Power VS 3.3 V Power Pins.
2
I
3.3 V CMOS
REFMON
Reference Monitor (Output). This pin has multiple selectable outputs; see Table 54,
Register 0x01B.
3 O 3.3 V CMOS LD Lock Detect (Output). This pin has multiple selectable outputs; see Table 54,
Register 0x1A.
4 I Power VCP Power Supply for Charge Pump (CP); V
S
≤ V
CP
≤ 5.0 V.
5
O
3.3 V CMOS
CP
Charge Pump (Output). Connects to external loop filter.
6 O 3.3 V CMOS STATUS Status (Output). This pin has multiple selectable outputs; see Table 54, Register 0x017.
7 I 3.3 V CMOS REF_SEL Reference Select. Selects REF1 (low) or REF2 (high). This pin has an internal 30 kΩ
pull-down resistor.
8 I 3.3 V CMOS
SYNC
Manual Synchronizations and Manual Holdover. This pin initiates a manual
synchronization and is also used for manual holdover. Active low. This pin has an
internal 30 kΩ pull-up resistor.
9 I Loop filter LF Loop Filter (Input). Connects to VCO control voltage node internally. This pin has
31 pF of internal capacitance to ground, which may influence the loop filter design
for large (>500 kHz) loop bandwidths.
10 O Loop filter BYPASS This pin is for bypassing the LDO to ground with a capacitor.
13 I Differential
clock input
CLK Along with
CLK
, this is the differential input for the clock distribution section.
14 I Differential
clock input
CLK
Along with CLK, this is the differential input for the clock distribution section.