Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Functional Block Diagram
- Revision History
- Specifications
- Power Supply Requirements
- PLL Characteristics
- Clock Inputs
- Clock Outputs
- Timing Characteristics
- Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used)
- Clock Output Absolute Phase Noise (Internal VCO Used)
- Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Cleanup Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Generation Using External VCXO)
- Clock Output Additive Time Jitter (VCO Divider Not Used)
- Clock Output Additive Time Jitter (VCO Divider Used)
- Delay Block Additive Time Jitter
- Serial Control Port
- PD, RESET, and SYNC Pins
- LD, STATUS, and REFMON Pins
- Power Dissipation
- Timing Diagrams
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Detailed Block Diagram
- Theory of Operation
- Operational Configurations
- High Frequency Clock Distribution—CLK or External VCO > 1600 MHz
- Internal VCO and Clock Distribution
- Clock Distribution or External VCO < 1600 MHz
- Phase-Locked Loop (PLL)
- Configuration of the PLL
- Phase Frequency Detector (PFD)
- Charge Pump (CP)
- On-Chip VCO
- PLL External Loop Filter
- PLL Reference Inputs
- Reference Switchover
- Reference Divider R
- VCXO/VCO Feedback Divider N—P, A, B, R
- Digital Lock Detect (DLD)
- Clock Distribution
- Reset Modes
- Power-Down Modes
- Operational Configurations
- Serial Control Port
- Thermal Performance
- Register Map Overview
- Register Map Descriptions
- Applications Information
- Outline Dimensions
Data Sheet AD9516-1
Rev. C | Page 9 of 80
Parameter Min Typ Max Unit Test Conditions/Comments
CLK = 1 GHz, Output = 50 MHz Input slew rate > 1 V/ns
Divider = 20
At 10 Hz Offset −124 dBc/Hz
At 100 Hz Offset −134 dBc/Hz
At 1 kHz Offset
−142
dBc/Hz
At 10 kHz Offset −151 dBc/Hz
At 100 kHz Offset −157 dBc/Hz
At 1 MHz Offset −160 dBc/Hz
>10 MHz Offset −163 dBc/Hz
CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED)
Table 7.
Parameter Min Typ Max Unit Test Conditions/Comments
LVPECL ABSOLUTE PHASE NOISE Internal VCO; direct to LVPECL output
VCO = 2.65 GHz; Output = 2.65 GHz
At 1 kHz Offset −46 dBc/Hz
At 10 kHz Offset −76 dBc/Hz
At 100 kHz Offset −104 dBc/Hz
At 1 MHz Offset −123 dBc/Hz
At 10 MHz Offset −140 dBc/Hz
At 40 MHz Offset −146 dBc/Hz
VCO = 2.475 GHz; Output = 2.475 GHz
At 1 kHz Offset −47 dBc/Hz
At 10 kHz Offset −77 dBc/Hz
At 100 kHz Offset −105 dBc/Hz
At 1 MHz Offset −124 dBc/Hz
At 10 MHz Offset −141 dBc/Hz
At 40 MHz Offset −146 dBc/Hz
VCO = 2.3 GHz; Output = 2.3 GHz
At 1 kHz Offset −54 dBc/Hz
At 10 kHz Offset −78 dBc/Hz
At 100 kHz Offset −106 dBc/Hz
At 1 MHz Offset −125 dBc/Hz
At 10 MHz Offset −141 dBc/Hz
At 40 MHz Offset −146 dBc/Hz