Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Functional Block Diagram
- Revision History
- Specifications
- Power Supply Requirements
- PLL Characteristics
- Clock Inputs
- Clock Outputs
- Timing Characteristics
- Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used)
- Clock Output Absolute Phase Noise (Internal VCO Used)
- Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Cleanup Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Generation Using External VCXO)
- Clock Output Additive Time Jitter (VCO Divider Not Used)
- Clock Output Additive Time Jitter (VCO Divider Used)
- Delay Block Additive Time Jitter
- Serial Control Port
- PD, RESET, and SYNC Pins
- LD, STATUS, and REFMON Pins
- Power Dissipation
- Timing Diagrams
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Detailed Block Diagram
- Theory of Operation
- Operational Configurations
- High Frequency Clock Distribution—CLK or External VCO > 1600 MHz
- Internal VCO and Clock Distribution
- Clock Distribution or External VCO < 1600 MHz
- Phase-Locked Loop (PLL)
- Configuration of the PLL
- Phase Frequency Detector (PFD)
- Charge Pump (CP)
- On-Chip VCO
- PLL External Loop Filter
- PLL Reference Inputs
- Reference Switchover
- Reference Divider R
- VCXO/VCO Feedback Divider N—P, A, B, R
- Digital Lock Detect (DLD)
- Clock Distribution
- Reset Modes
- Power-Down Modes
- Operational Configurations
- Serial Control Port
- Thermal Performance
- Register Map Overview
- Register Map Descriptions
- Applications Information
- Outline Dimensions
Data Sheet AD9516-1
Rev. C | Page 73 of 80
Reg.
Addr.
(Hex) Bits Name Description
0x143 [2:1] OUT9 LVDS output current Sets output current level in LVDS mode. This has no effect in CMOS mode.
2 1 Current (mA) Recommended Termination (Ω)
0 0 1.75 100
0 1 3.5 100 (default)
1 0 5.25 50
1 1 7 50
0 OUT9 power-down Power-down output (LVDS/CMOS).
0: power on.
1: power off (default).
Table 58. LVPECL Channel Dividers
Reg.
Addr.
(Hex)
Bits Name Description
0x190 [7:4] Divider 0 low cycles Number of clock cycles (minus 1) of the divider input during which divider output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
[3:0] Divider 0 high cycles Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
0x191 7 Divider 0 bypass Bypasses and powers down the divider; routes input to divider output.
0: uses divider.
1: bypasses divider (default).
6 Divider 0 nosync Nosync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
5 Divider 0 force high Forces divider output to high. This requires that nosync (Bit 6) also be set.
0: divider output forced to low (default).
1: divider output forced to high.
4 Divider 0 start high Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
[3:0] Divider 0 phase offset Phase offset (default = 0x0).
0x192 1 Divider 0 direct to output Connect OUT0 and OUT1 to Divider 0 or directly to VCO or CLK.
0: OUT0 and OUT1 are connected to Divider 0 (default).
1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT0 and OUT1.
If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT0 and OUT1.
If Register 0x1E1[1:0] = 01b, there is no effect.
0 Divider 0 DCCOFF Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
0x193 [7:4] Divider 1 low cycles Number of clock cycles of the divider input during which divider output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
[3:0] Divider 1 high cycles Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
0x194 7 Divider 1 bypass Bypasses and powers down the divider; routes input to divider output.
0: uses divider (default).
1: bypasses divider.
6 Divider 1 nosync Nosync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
5 Divider 1 force high Forces divider output to high. This requires that nosync (Bit 6) also be set.
0: divider output forced to low (default).
1: divider output forced to high.