Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Functional Block Diagram
- Revision History
- Specifications
- Power Supply Requirements
- PLL Characteristics
- Clock Inputs
- Clock Outputs
- Timing Characteristics
- Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used)
- Clock Output Absolute Phase Noise (Internal VCO Used)
- Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Cleanup Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Generation Using External VCXO)
- Clock Output Additive Time Jitter (VCO Divider Not Used)
- Clock Output Additive Time Jitter (VCO Divider Used)
- Delay Block Additive Time Jitter
- Serial Control Port
- PD, RESET, and SYNC Pins
- LD, STATUS, and REFMON Pins
- Power Dissipation
- Timing Diagrams
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Detailed Block Diagram
- Theory of Operation
- Operational Configurations
- High Frequency Clock Distribution—CLK or External VCO > 1600 MHz
- Internal VCO and Clock Distribution
- Clock Distribution or External VCO < 1600 MHz
- Phase-Locked Loop (PLL)
- Configuration of the PLL
- Phase Frequency Detector (PFD)
- Charge Pump (CP)
- On-Chip VCO
- PLL External Loop Filter
- PLL Reference Inputs
- Reference Switchover
- Reference Divider R
- VCXO/VCO Feedback Divider N—P, A, B, R
- Digital Lock Detect (DLD)
- Clock Distribution
- Reset Modes
- Power-Down Modes
- Operational Configurations
- Serial Control Port
- Thermal Performance
- Register Map Overview
- Register Map Descriptions
- Applications Information
- Outline Dimensions
AD9516-1 Data Sheet
Rev. C | Page 72 of 80
Reg.
Addr.
(Hex) Bits Name Description
0x141 0 OUT7 power-down Power-down output (LVDS/CMOS).
0: power on.
1: power off (default).
0x142
[7:5]
OUT8 output polarity
In CMOS mode, Bits[7:5] select the output polarity of each CMOS output.
In LVDS mode, only Bit 5 determines LVDS polarity.
7 6 5 OUT6A (CMOS) OUT6B (CMOS) OUT6 (LVDS)
0 0 0 Noninverting Inverting Noninverting
0 1 0 Noninverting Noninverting Noninverting (default)
1 0 0 Inverting Inverting Noninverting
1 1 0 Inverting Noninverting Noninverting
0 0 1 Inverting Noninverting Inverting
0 1 1 Inverting Inverting Inverting
1 0 1 Noninverting Noninverting Inverting
1 1 1 Noninverting Inverting Inverting
4 OUT8 CMOS B In CMOS mode, turns on/off the CMOS B output. There is no effect in LVDS mode.
0: turn off the CMOS B output (default).
1: turn on the CMOS B output.
3 OUT8 select LVDS/CMOS Selects LVDS or CMOS logic levels.
0: LVDS (default).
1: CMOS.
[2:1] OUT8 LVDS output current Sets output current level in LVDS mode. This has no effect in CMOS mode.
2 1 Current (mA) Recommended Termination (Ω)
0 0 1.75 100
0 1 3.5 100 (default)
1
0
5.25
50
1 1 7 50
0
OUT8 power-down
Power-down output (LVDS/CMOS).
0: power on (default).
1: power off.
0x143 [7:5] OUT9 output polarity In CMOS mode, Bits[7:5] select the output polarity of each CMOS output.
In LVDS mode, only Bit 5 determines LVDS polarity.
7 6 5 OUT7A (CMOS) OUT7B (CMOS) OUT7 (LVDS)
0 0 0 Noninverting Inverting Noninverting
0 1 0 Noninverting Noninverting Noninverting (default)
1 0 0 Inverting Inverting Noninverting
1 1 0 Inverting Noninverting Noninverting
0 0 1 Inverting Noninverting Inverting
0 1 1 Inverting Inverting Inverting
1 0 1 Noninverting Noninverting Inverting
1 1 1 Noninverting Inverting Inverting
4 OUT9 CMOS B In CMOS mode, turns on/off the CMOS B output. There is no effect in LVDS mode.
0: turn off the CMOS B output (default).
1: turn on the CMOS B output.
3 OUT9 select LVDS/CMOS Selects LVDS or CMOS logic levels.
0: LVDS (default).
1: CMOS.