Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Functional Block Diagram
- Revision History
- Specifications
- Power Supply Requirements
- PLL Characteristics
- Clock Inputs
- Clock Outputs
- Timing Characteristics
- Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used)
- Clock Output Absolute Phase Noise (Internal VCO Used)
- Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Cleanup Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Generation Using External VCXO)
- Clock Output Additive Time Jitter (VCO Divider Not Used)
- Clock Output Additive Time Jitter (VCO Divider Used)
- Delay Block Additive Time Jitter
- Serial Control Port
- PD, RESET, and SYNC Pins
- LD, STATUS, and REFMON Pins
- Power Dissipation
- Timing Diagrams
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Detailed Block Diagram
- Theory of Operation
- Operational Configurations
- High Frequency Clock Distribution—CLK or External VCO > 1600 MHz
- Internal VCO and Clock Distribution
- Clock Distribution or External VCO < 1600 MHz
- Phase-Locked Loop (PLL)
- Configuration of the PLL
- Phase Frequency Detector (PFD)
- Charge Pump (CP)
- On-Chip VCO
- PLL External Loop Filter
- PLL Reference Inputs
- Reference Switchover
- Reference Divider R
- VCXO/VCO Feedback Divider N—P, A, B, R
- Digital Lock Detect (DLD)
- Clock Distribution
- Reset Modes
- Power-Down Modes
- Operational Configurations
- Serial Control Port
- Thermal Performance
- Register Map Overview
- Register Map Descriptions
- Applications Information
- Outline Dimensions
Data Sheet AD9516-1
Rev. C | Page 69 of 80
Reg.
Addr.
(Hex) Bits Name Description
0x0F1 4 OUT1 invert Sets the output polarity.
0: noninverting (default).
1: inverting.
[3:2]
OUT1 LVPECL
Sets the LVPECL output differential voltage (V
OD
).
differential voltage
3 2 V
OD
(mV)
0 0 400
0 1 600
1 0 780 (default)
1
1
960
[1:0] OUT1 power-down LVPECL power-down modes.
1 0 Mode Output
0 0 Normal operation. On
0 1 Partial power-down, reference on; use only if there are no external load
resistors.
Off
1 0 Partial power-down, reference on, safe LVPECL power-down (default). Off
1 1 Total power-down, reference off; use only if there are no external load
resistors.
Off
0x0F2 4 OUT2 invert Sets the output polarity.
0: noninverting (default).
1: inverting.
[3:2] OUT2 LVPECL Sets the LVPECL output differential voltage (V
OD
).
differential voltage
3 2 V
OD
(mV)
0 0 400
0 1 600
1 0 780 (default)
1 1 960
[1:0] OUT2 power-down LVPECL power-down modes.
1 0 Mode Output
0 0 Normal operation (default). On
0 1 Partial power-down, reference on; use only if there are no external load
resistors.
Off
1 0 Partial power-down, reference on, safe LVPECL power-down. Off
1 1 Total power-down, reference off; use only if there are no external load
resistors.
Off
0x0F3 4 OUT3 invert Sets the output polarity.
0: noninverting (default).
1: inverting.
[3:2] OUT3 LVPECL Sets the LVPECL output differential voltage (V
OD
).
differential voltage
3 2 V
OD
(mV)
0 0 400
0 1 600
1 0 780 (default)
1 1 960
[1:0] OUT3 power-down LVPECL power-down modes.
1 0 Mode Output
0 0 Normal operation. On
0 1 Partial power-down, reference on; use only if there are no external
load resistors.
Off
1 0 Partial power-down, reference on, safe LVPECL power-down (default). Off
1 1 Total power-down, reference off; use only if there are no external
load resistors.
Off