Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Functional Block Diagram
- Revision History
- Specifications
- Power Supply Requirements
- PLL Characteristics
- Clock Inputs
- Clock Outputs
- Timing Characteristics
- Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used)
- Clock Output Absolute Phase Noise (Internal VCO Used)
- Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Cleanup Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Generation Using External VCXO)
- Clock Output Additive Time Jitter (VCO Divider Not Used)
- Clock Output Additive Time Jitter (VCO Divider Used)
- Delay Block Additive Time Jitter
- Serial Control Port
- PD, RESET, and SYNC Pins
- LD, STATUS, and REFMON Pins
- Power Dissipation
- Timing Diagrams
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Detailed Block Diagram
- Theory of Operation
- Operational Configurations
- High Frequency Clock Distribution—CLK or External VCO > 1600 MHz
- Internal VCO and Clock Distribution
- Clock Distribution or External VCO < 1600 MHz
- Phase-Locked Loop (PLL)
- Configuration of the PLL
- Phase Frequency Detector (PFD)
- Charge Pump (CP)
- On-Chip VCO
- PLL External Loop Filter
- PLL Reference Inputs
- Reference Switchover
- Reference Divider R
- VCXO/VCO Feedback Divider N—P, A, B, R
- Digital Lock Detect (DLD)
- Clock Distribution
- Reset Modes
- Power-Down Modes
- Operational Configurations
- Serial Control Port
- Thermal Performance
- Register Map Overview
- Register Map Descriptions
- Applications Information
- Outline Dimensions
AD9516-1 Data Sheet
Rev. C | Page 64 of 80
Reg.
Addr.
(Hex)
Bits Name Description
0x01B [4:0] REFMON Selects the signal that is connected to the REFMON pin.
pin control
4 3 2 1 0
Level or
Dynamic
Signal
Signal at REFMON Pin
0 0 0 0 0 LVL Ground (dc) (default).
0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode).
0 0 0 1 0 DYN REF2 clock (not available in differential mode).
0 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode).
0 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode).
0 0 1 0 1 LVL Status of selected reference (status of differential reference); active high.
0 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active high.
0 0 1 1 1 LVL Status REF1 frequency (active high).
0 1 0 0 0 LVL Status REF2 frequency (active high).
0 1 0 0 1 LVL (Status REF1 frequency) AND (status REF2 frequency).
0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO).
0 1 0 1 1 LVL Status of VCO frequency (active high).
0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2).
0 1 1 0 1 LVL Digital lock detect (DLD); active low.
0 1 1 1 0 LVL Holdover active (active high).
0 1 1 1 1 LVL LD pin comparator output (active high).
1 0 0 0 0 LVL VS (PLL supply).
1 0 0 0 1 DYN
REF1 clock
(differential reference when in differential mode).
1 0 0 1 0 DYN
REF2 clock
(not available in differential mode).
1 0 0 1 1 DYN
Selected reference to PLL
(differential reference when in differential mode).
1
0
1
0
0
DYN
Unselected reference to PLL
(not available when in differential mode).
1 0 1 0 1 LVL Status of selected reference (status of differential reference); active low.
1 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active low.
1 0 1 1 1 LVL Status of REF1 frequency (active low).
1 1 0 0 0 LVL Status of REF2 frequency (active low).
1 1 0 0 1 LVL
(Status of REF1 frequency) AND (Status of REF2 frequency)
.
1 1 0 1 0 LVL
(DLD) AND (Status of selected reference) AND (Status of VCO)
.
1 1 0 1 1 LVL Status of VCO frequency (active low).
1 1 1 0 0 LVL Selected reference (low = REF2, high = REF1).
1 1 1 0 1 LVL Digital lock detect (DLD); active low.
1 1 1 1 0 LVL Holdover active (active low).
1 1 1 1 1 LVL LD pin comparator output (active low).
0x01C 7 Disable Disables or enables the switchover deglitch circuit.
switchover 0: enables switchover deglitch circuit (default).
deglitch 1: disables switchover deglitch circuit.
6 Select REF2 If Register 0x01C, Bit 5 = 0, select reference for PLL.
0: selects REF1 (default).
1: selects REF2.
5 Use REF_SEL pin Sets method of PLL reference selection.
0: uses Register 0x01C, Bit 6 (default).
1: uses REF_SEL pin.
4
Reserved
0: (default).
3 Reserved 0: (default).
2 REF2 power-on This bit turns the REF2 power on.
0: REF2 power off (default).
1: REF2 power on.
1 REF1 power-on This bit turns the REF1 power on.
0: REF1 power off (default).
1: REF1 power on.
0
Differential
reference
Selects the PLL reference mode, differential or single-ended. Single-ended must be selected for the automatic
switchover or REF1 and REF2 to work.
0: single-ended reference mode (default).
1: differential reference mode.