Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Functional Block Diagram
- Revision History
- Specifications
- Power Supply Requirements
- PLL Characteristics
- Clock Inputs
- Clock Outputs
- Timing Characteristics
- Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used)
- Clock Output Absolute Phase Noise (Internal VCO Used)
- Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Cleanup Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Generation Using External VCXO)
- Clock Output Additive Time Jitter (VCO Divider Not Used)
- Clock Output Additive Time Jitter (VCO Divider Used)
- Delay Block Additive Time Jitter
- Serial Control Port
- PD, RESET, and SYNC Pins
- LD, STATUS, and REFMON Pins
- Power Dissipation
- Timing Diagrams
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Detailed Block Diagram
- Theory of Operation
- Operational Configurations
- High Frequency Clock Distribution—CLK or External VCO > 1600 MHz
- Internal VCO and Clock Distribution
- Clock Distribution or External VCO < 1600 MHz
- Phase-Locked Loop (PLL)
- Configuration of the PLL
- Phase Frequency Detector (PFD)
- Charge Pump (CP)
- On-Chip VCO
- PLL External Loop Filter
- PLL Reference Inputs
- Reference Switchover
- Reference Divider R
- VCXO/VCO Feedback Divider N—P, A, B, R
- Digital Lock Detect (DLD)
- Clock Distribution
- Reset Modes
- Power-Down Modes
- Operational Configurations
- Serial Control Port
- Thermal Performance
- Register Map Overview
- Register Map Descriptions
- Applications Information
- Outline Dimensions
Data Sheet AD9516-1
Rev. C | Page 63 of 80
Reg.
Addr.
(Hex)
Bits Name Description
0x01A [5:0] LD pin control Selects the signal that is connected to the LD pin.
5 4 3 2 1 0
Level or
Dynamic
Signal
Signal at LD Pin
0 0 0 0 0 0 LVL Digital lock detect (high = lock, low = unlock) (default).
0 0 0 0 0 1 DYN P-channel, open-drain lock detect (analog lock detect).
0 0 0 0 1 0 DYN N-channel, open-drain lock detect (analog lock detect).
0 0 0 0 1 1 HIZ High-Z LD pin.
0 0 0 1 0 0 CUR Current source lock detect (110 µA when DLD is true).
0 X X X X X LVL Ground (dc); for all other cases of 0XXXXX not specified above.
The selections that follow are the same as REFMON.
1 0 0 0 0 0 LVL Ground (dc).
1
0
0
0
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
0
0
0
1
0
DYN
REF2 clock (not available in differential mode).
1 0 0 0 1 1 DYN Selected reference to PLL (differential reference when indifferential mode).
1 0 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode).
1 0 0 1 0 1 LVL Status of selected reference (status of differential reference); active high.
1 0 0 1 1 0 LVL
Status of unselected reference (not available in differential mode); active
high.
1 0 0 1 1 1 LVL Status REF1 frequency (active high).
1 0 1 0 0 0 LVL Status REF2 frequency (active high).
1 0 1 0 0 1 LVL (Status REF1 frequency) AND (status REF2 frequency).
1 0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO).
1 0 1 0 1 1 LVL Status of VCO frequency (active high).
1 0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2).
1 0 1 1 0 1 LVL Digital lock detect (DLD); active high.
1 0 1 1 1 0 LVL Holdover active (active high).
1 0 1 1 1 1 LVL Not available. Do not use.
1 1 0 0 0 0 LVL VS (PLL supply).
1 1 0 0 0 1 DYN
REF1 clock
(differential reference when in differential mode).
1 1 0 0 1 0 DYN
REF2 clock
(not available in differential mode).
1
1
0
0
1
1
DYN
Selected reference to PLL
(differential reference when in differential mode).
1 1 0 1 0 0 DYN
Unselected reference to PLL
(not available when in differential mode).
1
1
0
1
0
1
LVL
Status of selected reference (status of differential reference); active low.
1
1
0
1
1
0
LVL
Status of unselected reference (not available in differential mode); active
low.
1 1 0 1 1 1 LVL Status of REF1 frequency (active low).
1 1 1 0 0 0 LVL Status of REF2 frequency (active low).
1 1 1 0 0 1 LVL
(Status of REF1 frequency) AND (status of REF2 frequency)
.
1 1 1 0 1 0 LVL
(DLD) AND (status of selected reference) AND (status of VCO)
.
1 1 1 0 1 1 LVL Status of VCO frequency (active low).
1 1 1 1 0 0 LVL Selected reference (low = REF2, high = REF1).
1 1 1 1 0 1 LVL Digital lock detect (DLD); active low.
1 1 1 1 1 0 LVL Holdover active (active low).
1 1 1 1 1 1 LVL Not available. Do not use.
0x01B 7 VCO frequency Enables or disables VCO frequency monitor.
monitor 0: disables VCO frequency monitor (default).
1: enables VCO frequency monitor.
6
REF2 (
REFIN
)
Enables or disables REF2 frequency monitor.
frequency monitor 0: disables REF2 frequency monitor (default).
1: enables REF2 frequency monitor.
5
REF1 (REFIN)
frequency monitor
REF1 (REFIN) frequency monitor enable; this is for both REF1 (single-ended) and REFIN (differential) inputs
(as selected by differential reference mode).
0: disables REF1 (REFIN) frequency monitor (default).
1: enables REF1 (REFIN) frequency monitor.