Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Functional Block Diagram
- Revision History
- Specifications
- Power Supply Requirements
- PLL Characteristics
- Clock Inputs
- Clock Outputs
- Timing Characteristics
- Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used)
- Clock Output Absolute Phase Noise (Internal VCO Used)
- Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Cleanup Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Generation Using External VCXO)
- Clock Output Additive Time Jitter (VCO Divider Not Used)
- Clock Output Additive Time Jitter (VCO Divider Used)
- Delay Block Additive Time Jitter
- Serial Control Port
- PD, RESET, and SYNC Pins
- LD, STATUS, and REFMON Pins
- Power Dissipation
- Timing Diagrams
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Detailed Block Diagram
- Theory of Operation
- Operational Configurations
- High Frequency Clock Distribution—CLK or External VCO > 1600 MHz
- Internal VCO and Clock Distribution
- Clock Distribution or External VCO < 1600 MHz
- Phase-Locked Loop (PLL)
- Configuration of the PLL
- Phase Frequency Detector (PFD)
- Charge Pump (CP)
- On-Chip VCO
- PLL External Loop Filter
- PLL Reference Inputs
- Reference Switchover
- Reference Divider R
- VCXO/VCO Feedback Divider N—P, A, B, R
- Digital Lock Detect (DLD)
- Clock Distribution
- Reset Modes
- Power-Down Modes
- Operational Configurations
- Serial Control Port
- Thermal Performance
- Register Map Overview
- Register Map Descriptions
- Applications Information
- Outline Dimensions
Data Sheet AD9516-1
Rev. C | Page 57 of 80
Reg.
Addr.
(Hex)
Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
Default
Value
(Hex)
0x144
to
0x18F
Blank
LVPECL Channel Dividers
0x190
Divider 0
(PECL)
Divider 0 low cycles Divider 0 high cycles 0x00
0x191
Divider 0
bypass
Divider 0
no sync
Divider 0
force high
Divider 0
start high
Divider 0 phase offset 0x80
0x192 Blank Reserved
Divider 0
direct to
output
Divider 0
DCCOFF
0x00
0x193
Divider 1
(PECL)
Divider 1 low cycles Divider 1 high cycles 0xBB
0x194
Divider 1
bypass
Divider 1
no sync
Divider 1
force high
Divider 1
start high
Divider 1 phase offset 0x00
0x195 Blank Reserved
Divider 1
direct to
output
Divider 1
DCCOFF
0x00
0x196
Divider 2
(PECL)
Divider 2 low cycles Divider 2 high cycles 0x00
0x197
Divider 2
bypass
Divider 2
no sync
Divider 2
force high
Divider 2
start high
Divider 2 phase offset 0x00
0x198 Blank Reserved
Divider 2
direct to
output
Divider 2
DCCOFF
0x00
LVDS/CMOS Channel Dividers
0x199
Divider 3
(LVDS/CMOS)
Low Cycles Divider 3.1 High Cycles Divider 3.1 0x22
0x19A Phase Offset Divider 3.2 Phase Offset Divider 3.1 0x00
0x19B Low Cycles Divider 3.2 High Cycles Divider 3.2 0x11
0x19C
Reserved
Bypass
Divider 3.2
Bypass
Divider 3.1
Divider 3
no sync
Divider 3
force high
Start High
Divider 3.2
Start High
Divider 3.1
0x00
0x19D Blank Reserved
Divider 3
DCCOFF
0x00
0x19E
Divider 4
(LVDS/CMOS)
Low Cycles Divider 4.1 High Cycles Divider 4.1 0x22
0x19F Phase Offset Divider 4.2 Phase Offset Divider 4.1 0x00
0x1A0 Low Cycles Divider 4.2 High Cycles Divider 4.2 0x11
0x1A1 Reserved
Bypass
Divider 4.2
Bypass
Divider 4.1
Divider 4
no sync
Divider 4
force high
Start High
Divider 4.2
Start High
Divider 4.1
0x00
0x1A2 Blank Reserved
Divider 4
DCCOFF
0x00
0x1A3
Reserved
0x1A4
to
0x1DF
Blank
VCO Divider and CLK Input
0x1E0 VCO divider Blank Reserved VCO Divider 0x02
0x1E1 Input CLKs Reserved
Power-
down
clock input
section
Power-down
VCO clock
interface
Power-
down VCO
and CLK
Select
VCO or CLK
Bypass VCO
divider
0x00
0x1E2
to
0x22A
Blank