Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Functional Block Diagram
- Revision History
- Specifications
- Power Supply Requirements
- PLL Characteristics
- Clock Inputs
- Clock Outputs
- Timing Characteristics
- Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used)
- Clock Output Absolute Phase Noise (Internal VCO Used)
- Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Cleanup Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Generation Using External VCXO)
- Clock Output Additive Time Jitter (VCO Divider Not Used)
- Clock Output Additive Time Jitter (VCO Divider Used)
- Delay Block Additive Time Jitter
- Serial Control Port
- PD, RESET, and SYNC Pins
- LD, STATUS, and REFMON Pins
- Power Dissipation
- Timing Diagrams
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Detailed Block Diagram
- Theory of Operation
- Operational Configurations
- High Frequency Clock Distribution—CLK or External VCO > 1600 MHz
- Internal VCO and Clock Distribution
- Clock Distribution or External VCO < 1600 MHz
- Phase-Locked Loop (PLL)
- Configuration of the PLL
- Phase Frequency Detector (PFD)
- Charge Pump (CP)
- On-Chip VCO
- PLL External Loop Filter
- PLL Reference Inputs
- Reference Switchover
- Reference Divider R
- VCXO/VCO Feedback Divider N—P, A, B, R
- Digital Lock Detect (DLD)
- Clock Distribution
- Reset Modes
- Power-Down Modes
- Operational Configurations
- Serial Control Port
- Thermal Performance
- Register Map Overview
- Register Map Descriptions
- Applications Information
- Outline Dimensions
Data Sheet AD9516-1
Rev. C | Page 55 of 80
REGISTER MAP OVERVIEW
Table 52. Register Map Overview
Reg.
Addr.
(Hex) Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
Default
Value
(Hex)
Serial Port Configuration
0x000
Serial port
configuration
SDO
active
LSB first Soft reset
Long
instruction
Long
instruction
Soft reset LSB first SDO active 0x18
0x001 Blank
0x002 Reserved
0x003
Part ID
Part ID (read only)
0x01
0x004
Readback
control
Blank
Read back
active
registers
0x00
PLL
0x010
PFD and
charge pump
PFD
polarity
Charge pump current Charge pump mode PLL power-down 0x7D
0x011 R counter 14-bit R divider, Bits[7:0] (LSB) 0x01
0x012 Blank 14-bit R divider, Bits[13:8] (MSB) 0x00
0x013 A counter Blank 6-bit A counter 0x00
0x014 B counter 13-bit B counter, Bits[7:0] (LSB) 0x03
0x015 Blank 13-bit B counter, Bits[12:8] (MSB) 0x00
0x016 PLL Control 1
Set CP pin
to V
CP
/2
Reset R
counter
Reset A and
B counters
Reset all
counters
B counter
bypass
Prescaler P 0x06
0x017 PLL Control 2 STATUS pin control Antibacklash pulse width 0x00
0x018 PLL Control 3 Reserved Lock detect counter
Digital lock
detect
window
Disable
digital lock
detect
VCO calibration divider VCO cal now 0x06
0x019 PLL Control 4
R, A, B counters
SYNC
pin reset
R path delay N path delay 0x00
0x01A PLL Control 5 Reserved
Reference
frequency
monitor
threshold
LD pin control 0x00
0x01B PLL Control 6
VCO
frequency
monitor
REF2
(
REFIN
)
frequency
monitor
REF1 (REFIN)
frequency
monitor
REFMON pin control 0x00
0x01C
PLL Control 7
Disable
switchover
deglitch
Select
REF2
Use
REF_SEL pin
Reserved
Reserved
REF2
power-on
REF1
power-on
Differential
reference
0x00
0x01D PLL Control 8 Reserved
PLL status
register
disable
LD pin
comparator
enable
Holdover
enable
External
holdover
control
Holdover
enable
0x00
0x01E PLL Control 9 Reserved 0x00
0x01F PLL readback Reserved
VCO cal
finished
Holdover
active
REF2
selected
VCO
frequency >
threshold
REF2
frequency >
threshold
REF1
frequency >
threshold
Digital
lock detect
N/A
0x020
to
0x04F
Blank