Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Functional Block Diagram
- Revision History
- Specifications
- Power Supply Requirements
- PLL Characteristics
- Clock Inputs
- Clock Outputs
- Timing Characteristics
- Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used)
- Clock Output Absolute Phase Noise (Internal VCO Used)
- Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Cleanup Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Generation Using External VCXO)
- Clock Output Additive Time Jitter (VCO Divider Not Used)
- Clock Output Additive Time Jitter (VCO Divider Used)
- Delay Block Additive Time Jitter
- Serial Control Port
- PD, RESET, and SYNC Pins
- LD, STATUS, and REFMON Pins
- Power Dissipation
- Timing Diagrams
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Detailed Block Diagram
- Theory of Operation
- Operational Configurations
- High Frequency Clock Distribution—CLK or External VCO > 1600 MHz
- Internal VCO and Clock Distribution
- Clock Distribution or External VCO < 1600 MHz
- Phase-Locked Loop (PLL)
- Configuration of the PLL
- Phase Frequency Detector (PFD)
- Charge Pump (CP)
- On-Chip VCO
- PLL External Loop Filter
- PLL Reference Inputs
- Reference Switchover
- Reference Divider R
- VCXO/VCO Feedback Divider N—P, A, B, R
- Digital Lock Detect (DLD)
- Clock Distribution
- Reset Modes
- Power-Down Modes
- Operational Configurations
- Serial Control Port
- Thermal Performance
- Register Map Overview
- Register Map Descriptions
- Applications Information
- Outline Dimensions
AD9516-1 Data Sheet
Rev. C | Page 52 of 80
Table 49. Serial Control Port, 16-Bit Instruction Word, MSB First
MSB LSB
I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0
R/W
W1 W0 A12 = 0 A11 = 0 A10 = 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
CS
SCLK
DON'T CARE
SDIO A12W0W1R/W A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
DON'T CARE
DON'T CARE
DON'T CARE
16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N – 1) DATA
0
6420-038
Figure 64. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes Data
CS
SCLK
SDIO
SDO
REGISTER (N) DATA16-BIT INSTRUCTION HEADER REGISTER (N – 1) DATA REGISTER (N – 2) DATA REGISTER (N – 3) DATA
A12W0W1R/W A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
DON'T CARE
DON'T CARE
DON'T CARE
DON'T
CARE
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
06420-039
Figure 65. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes Data
t
S
DON'T CARE
DON'T CARE
W1W0A12A11A10A9A8A7A6A5D4D3D2D1D0
DON'T CARE
DON'T CARE
R/W
t
DS
t
DH
t
HI
t
LO
t
CLK
t
C
CS
SCLK
SDIO
0
6420-040
Figure 66. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements
DATA BIT N – 1DATA BIT N
CS
SCLK
SDIO
SDO
t
DV
06420-041
Figure 67. Timing Diagram for Serial Control Port Register Read
CS
SCLK
DON'T CARE
DON'T CARE
16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N + 1) DATA
SDIO
DON'T CARE
DON'T CARE
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 D1D0R/WW1W0 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
0
6420-042
Figure 68. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes Data