Datasheet

Data Sheet AD9516-1
Rev. C | Page 45 of 80
Table 44. Divider 3, Divider 4 Duty Cycle; VCO Divider Not
Used; Duty Cycle Correction On (DCCOFF = 0)
Input
Clock
Duty
Cycle
D
X.1
D
X.2
Output
Duty Cycle
N
X.1
+ M
X.1
+ 2 N
X.2
+ M
X.2
+ 2
50% 1 1 50%
50% Even
(N
X.1
= M
X.1
)
1 50%
X% 1 1 X% (High)
X% Even
(N
X.1
= M
X.1
)
1 50%
50% Odd
(M
X.1
= N
X.1
+ 1)
1 50%
X% Odd
(M
X.1
= N
X.1
+ 1)
1 (N
X.1
+ 1 + X%)/
(2N
X.1
+ 3)
Odd
(M
X.1
= N
X.1
+ 1)
1 (N
X.1
+ 1 + X%)/
(2N
X.1
+ 3)
50% Even
(N
X.1
= M
X.1
)
Even
(N
X.2
= M
X.2
)
50%
X%
Even
(N
X.1
= M
X.1
)
Even
(N
X.2
= M
X.2
)
50%
50% Odd
(M
X.1
= N
X.1
+ 1)
Even
(N
X.2
= M
X.2
)
50%
X% Odd
(M
X.1
= N
X.1
+ 1)
Even
(N
X.2
= M
X.2
)
50%
50% Odd
(M
X.1
= N
X.1
+ 1)
Odd
(M
X.2
= N
X.2
+ 1)
50%
X% Odd
(M
X.1
= N
X.1
+ 1)
Odd
(M
X.2
= N
X.2
+ 1)
(2N
X.1
N
X.2
+ 3N
X.1
+
3N
X.2
+ 4 + X%)/
((2N
X.1
+ 3)(2N
X.2
+ 3))
Phase Offset or Coarse Time Delay (Divider 3 and Divider 4)
Divider 3 and Divider 4 can be set to have a phase offset or
delay. The phase offset is set by a combination of the bits in the
phase offset and start high registers (see Table 45).
Table 45. Setting Phase Offset and Division for Divider 3 and
Divider 4
Divider
Start
High (SH)
Phase
Offset (PO)
Low
Cycles M
High
Cycles N
3 3.1 0x19C[0] 0x19A[3:0] 0x199[7:4] 0x199[3:0]
3.2 0x19C[1] 0x19A[7:4] 0x19B[7:4] 0x19B[3:0]
4 4.1 0x1A1[0] 0x19F[3:0] 0x19E[7:4] 0x19E[3:0]
4.2 0x1A1[1] 0x19F[7:4] 0x1A0[7:4] 0x1A0[3:0]
Let Δt = delay (in seconds).
Φ
x.y
= 16 × SH[0] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] +
1 × PO[0].
T
X.1
= period of the clock signal at the input to D
X.1
(in seconds).
T
X.2
= period of the clock signal at the input to D
X.2
(in seconds).
Case 1
When Φ
x.1
≤ 15 and Φ
x.2
≤ 15:
Δt = Φ
x.1
× T
X.1
+ Φ
X.2
× T
x.2
Case 2
When Φ
x.1
≤ 15 and Φ
x.2
≥ 16:
Δt = Φ
X.1
× T
X.1
+ (Φ
X.2
− 16 + M
X.2
+ 1) × T
X.2
Case 3
When Φ
X.1
≥ 16 and Φ
X.2
≤ 15:
Δt = (Φ
X.1
− 16 + M
X.1
+ 1) × T
X.1
+ Φ
X.2
× T
X.2
Case 4
When Φ
X.1
≥ 16 and Φ
X.2
≥ 16:
Δt =
(Φ
X.1
− 16 + M
X.1
+ 1) × T
X.1
+ (Φ
X.2
− 16 + M
X.2
+ 1) × T
X.2
Fine Delay Adjust (Divider 3 and Divider 4)
Each AD9516 LVDS/CMOS output (OUT6 to OUT9) includes
an analog delay element that can be programmed to give
variable time delays (Δt) in the clock signal at that output.
DIVIDER
X.2
DIVIDER
X.1
Δt
OUTM
OUTM
BYPASS
FINE DELAY
ADJUST
CMOS
LVDS
CMOS
Δt
OUTN
OUTN
BYPASS
FINE DELAY
ADJUST
CMOS
LVDS
CMOS
OUTPUT
DRIVERS
CLK
VCO
DIVIDER
06420-072
Figure 56. Fine Delay (OUT6 to OUT9)
The amount of delay applied to the clock signal is determined
by programming four registers per output (see Table 46).
Table 46. Setting Analog Fine Delays
OUTPUT
(LVDS/CMOS)
Ramp
Capacitors
Ramp
Current
Delay
Fraction
Delay
Bypass
OUT6
0x0A1[5:3] 0x0A1[2:0] 0x0A2[5:0] 0x0A0[0]
OUT7
0x0A4[5:3] 0x0A4[2:0] 0x0A5[5:0] 0x0A3[0]
OUT8
0x0A7[5:3] 0x0A7[2:0] 0x0A8[5:0] 0x0A6[0]
OUT9
0x0AA[5:3] 0x0AA[2:0] 0x0AB[5:0] 0x0A9[0]