Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Functional Block Diagram
- Revision History
- Specifications
- Power Supply Requirements
- PLL Characteristics
- Clock Inputs
- Clock Outputs
- Timing Characteristics
- Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used)
- Clock Output Absolute Phase Noise (Internal VCO Used)
- Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Cleanup Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Generation Using External VCXO)
- Clock Output Additive Time Jitter (VCO Divider Not Used)
- Clock Output Additive Time Jitter (VCO Divider Used)
- Delay Block Additive Time Jitter
- Serial Control Port
- PD, RESET, and SYNC Pins
- LD, STATUS, and REFMON Pins
- Power Dissipation
- Timing Diagrams
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Detailed Block Diagram
- Theory of Operation
- Operational Configurations
- High Frequency Clock Distribution—CLK or External VCO > 1600 MHz
- Internal VCO and Clock Distribution
- Clock Distribution or External VCO < 1600 MHz
- Phase-Locked Loop (PLL)
- Configuration of the PLL
- Phase Frequency Detector (PFD)
- Charge Pump (CP)
- On-Chip VCO
- PLL External Loop Filter
- PLL Reference Inputs
- Reference Switchover
- Reference Divider R
- VCXO/VCO Feedback Divider N—P, A, B, R
- Digital Lock Detect (DLD)
- Clock Distribution
- Reset Modes
- Power-Down Modes
- Operational Configurations
- Serial Control Port
- Thermal Performance
- Register Map Overview
- Register Map Descriptions
- Applications Information
- Outline Dimensions

AD9516-1 Data Sheet
Rev. C | Page 44 of 80
Duty Cycle and Duty-Cycle Correction (Divider 3 and
Divider 4)
The same duty cycle and DCC considerations apply to Divider 3
and Divider 4 as to Divider 0, Divider 1, and Divider 2 (see the
Duty Cycle and Duty-Cycle Correction (0, 1, and 2) section);
however, with these channel dividers, the number of possible
configurations is even more complex.
Duty-cycle correction on Divider 3 and Divider 4 requires the
following channel divider conditions:
• An even D
X.Y
must be set as M
X.Y
= N
X.Y
(low cycles = high
cycles).
• An odd D
X.Y
must be set as M
X.Y
= N
X.Y
+ 1 (the number of
low cycles must be one greater than the number of high
cycles).
• If only one divider is bypassed, it must be the second
divider, X.2.
• If only one divider has an even divide by, it must be the
second divider, X.2.
The possibilities for the duty cycle of the output clock from
Divider 3 and Divider 4 are shown in Table 40 through Table 44
Table 40. Divider 3, Divider 4 Duty Cycle; VCO Divider
Used; Duty Cycle Correction Off (DCCOFF = 1)
VCO
Divider
D
X.1
D
X.2
Output Duty
Cycle
N
X.1
+ M
X.1
+ 2 N
X.2
+ M
X.2
+ 2
Even 1 1 50%
Odd = 3 1 1 33.3%
Odd = 5
1
1
40%
Even Even, odd 1 (N
X.1
+ 1)/
(N
X.1
+ M
X.1
+ 2)
Odd Even, odd 1 (N
X.1
+ 1)/
(N
X.1
+ M
X.1
+ 2)
Even Even, odd Even, odd (N
X.2
+ 1)/
(N
X.2
+ M
X.2
+ 2)
Odd Even, odd Even, odd (N
X.2
+ 1)/
(N
X.2
+ M
X.2
+ 2)
Table 41. Divider 3, Divider 4 Duty Cycle; VCO Divider Not
Used; Duty Cycle Correction Off (DCCOFF = 1)
Input Clock
Duty Cycle
D
X.1
D
X.2
Output
Duty Cycle
N
X.1
+ M
X.1
+ 2 N
X.2
+ M
X.2
+ 2
50% 1 1 50%
X% 1 1 X%
50% Even, odd 1 (N
X.1
+ 1)/
(N
X.1
+ M
X.1
+ 2)
X% Even, odd 1 (N
X.1
+ 1)/
(N
X.1
+ M
X.1
+ 2)
50% Even, odd Even, odd (N
X.2
+ 1)/
(N
X.2
+ M
X.2
+ 2)
X% Even, odd Even, odd (N
X.2
+ 1)/
(N
X.2
+ M
X.2
+ 2)
Table 42. Divider 3, Divider 4 Duty Cycle; VCO Divider
Used; Duty Cycle Correction Is On (DCCOFF = 0); VCO
Divider Input Duty Cycle = 50%
VCO
Divider
D
X.1
D
X.2
Output
Duty Cycle N
X.1
+ M
X.1
+ 2 N
X.2
+ M
X.2
+ 2
Even 1 1 50%
Odd 1 1 50%
Even Even (N
X.1
= M
X.1
) 1 50%
Odd Even (N
X.1
= M
X.1
) 1 50%
Even Odd (M
X.1
= N
X.1
+ 1) 1 50%
Odd Odd (M
X.1
= N
X.1
+ 1) 1 50%
Even Even (N
X.1
= M
X.1
) Even (N
X.2
= M
X.2
) 50%
Odd Even (N
X.1
= M
X.1
) Even (N
X.2
= M
X.2
) 50%
Even Odd (M
X.1
= N
X.1
+ 1) Even (N
X.2
= M
X.2
) 50%
Odd
Odd (M
X.1
= N
X.1
+ 1)
Even (N
X.2
= M
X.2
)
50%
Even Odd (M
X.1
= N
X.1
+ 1) Odd (M
X.2
= N
X.2
+ 1) 50%
Odd Odd (M
X.1
= N
X.1
+ 1) Odd (M
X.2
= N
X.2
+ 1) 50%
Table 43. Divider 3, Divider 4 Duty Cycle; VCO Divider
Used; Duty Cycle Correction On (DCCOFF = 0); VCO
Divider Input Duty Cycle = X%
VCO
Divider
D
X.1
D
X.2
Output
Duty Cycle
N
X.1
+ M
X.1
+ 2 N
X.2
+ M
X.2
+ 2
Even 1 1 50%
Odd = 3 1 1 (1 + X%)/3
Odd = 5 1 1 (2 + X%)/5
Even
Even
(N
X.1
= M
X.1
)
1 50%
Odd Even
(N
X.1
= M
X.1
)
1 50%
Even Odd
(M
X.1
= N
X.1
+ 1)
1 50%
Odd = 3 Odd
(M
X.1
= N
X.1
+ 1)
1
(3N
X.1
+ 4 + X%)/
(6N
X.1
+ 9)
Odd = 5 Odd
(M
X.1
= N
X.1
+ 1)
1
(5N
X.1
+ 7 + X%)/
(10N
X.1
+ 15)
Even Even
(N
X.1
= M
X.1
)
Even
(N
X.2
= M
X.2
)
50%
Odd Even
(N
X.1
= M
X.1
)
Even
(N
X.2
= M
X.2
)
50%
Even Odd
(M
X.1
= N
X.1
+ 1)
Even
(N
X.2
= M
X.2
)
50%
Odd Odd
(M
X.1
= N
X.1
+ 1)
Even
(N
X.2
= M
X.2
)
50%
Even Odd
(M
X.1
= N
X.1
+ 1)
Odd
(M
X.2
= N
X.2
+ 1)
50%
Odd = 3
Odd
(M
X.1
= N
X.1
+ 1)
Odd
(M
X.2
= N
X.2
+ 1)
(6N
X.1
N
X.2
+ 9N
X.1
+
9N
X.2
+ 13 + X%)/
(3(2N
X.1
+ 3)
(2N
X.2
+ 3))
Odd = 5
Odd
(M
X.1
= N
X.1
+ 1)
Odd
(M
X.2
= N
X.2
+ 1)
(10N
X.1
N
X.2
+ 15N
X.1
+
15N
X.2
+ 22 + X%)/
(5(2 N
X.1
+ 3)
(2 N
X.2
+ 3))