Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Functional Block Diagram
- Revision History
- Specifications
- Power Supply Requirements
- PLL Characteristics
- Clock Inputs
- Clock Outputs
- Timing Characteristics
- Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used)
- Clock Output Absolute Phase Noise (Internal VCO Used)
- Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Cleanup Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Generation Using External VCXO)
- Clock Output Additive Time Jitter (VCO Divider Not Used)
- Clock Output Additive Time Jitter (VCO Divider Used)
- Delay Block Additive Time Jitter
- Serial Control Port
- PD, RESET, and SYNC Pins
- LD, STATUS, and REFMON Pins
- Power Dissipation
- Timing Diagrams
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Detailed Block Diagram
- Theory of Operation
- Operational Configurations
- High Frequency Clock Distribution—CLK or External VCO > 1600 MHz
- Internal VCO and Clock Distribution
- Clock Distribution or External VCO < 1600 MHz
- Phase-Locked Loop (PLL)
- Configuration of the PLL
- Phase Frequency Detector (PFD)
- Charge Pump (CP)
- On-Chip VCO
- PLL External Loop Filter
- PLL Reference Inputs
- Reference Switchover
- Reference Divider R
- VCXO/VCO Feedback Divider N—P, A, B, R
- Digital Lock Detect (DLD)
- Clock Distribution
- Reset Modes
- Power-Down Modes
- Operational Configurations
- Serial Control Port
- Thermal Performance
- Register Map Overview
- Register Map Descriptions
- Applications Information
- Outline Dimensions
Data Sheet AD9516-1
Rev. C | Page 43 of 80
Phase Offset or Coarse Time Delay (0, 1, and 2)
Each channel divider allows for a phase offset, or a coarse time
delay, to be programmed by setting register bits (see Table 38).
These settings determine the number of cycles (successive
rising edges) of the channel divider input frequency by which to
offset or delay the rising edge of the output of the divider. This
delay is with respect to a nondelayed output (that is, with a
phase offset of zero). The amount of the delay is set by five bits
loaded into the phase offset (PO) register, plus the start high
(SH) bit for each channel divider. When the start high bit is set,
the delay is also affected by the number of low cycles (M) that
are programmed for the divider.
The SYNC function must be used to make phase offsets effective
(see the Synchronizing the Outputs—SYNC Function section).
Table 38. Setting Phase Offset and Division for Divider 0,
Divider 1, and Divider 2
Divider
Start
High (SH)
Phase
Offset (PO)
Low
Cycles (M)
High
Cycles (N)
0 0x191[4] 0x191[3:0] 0x190[7:4] 0x190[3:0]
1 0x194[4] 0x194[3:0] 0x193[7:4] 0x193[3:0]
2 0x197[4] 0x197[3:0] 0x196[7:4] 0x196[3:0]
Let
Δt = delay (in seconds).
Δc = delay (in cycles of clock signal at input to D
X
).
T
X
= period of the clock signal at the input of the divider, D
X
(in seconds).
Φ = 16 × SH[4] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] + 1 × PO[0]
The channel divide-by is set as N = high cycles, and M = low cycles.
Case 1
For Φ ≤ 15:
Δt = Φ × T
X
Δc = Δt/T
X
= Φ
Case 2
For Φ ≥ 16:
Δt = (Φ − 16 + M + 1) × T
X
Δc = Δt/T
X
By giving each divider a different phase offset, output-to-output
delays can be set in increments of the channel divider input clock
cycle. Figure 55 shows the results of setting such a coarse offset
between outputs.
C
H
A
N
N
E
L
D
I
V
I
D
E
R
O
U
T
P
U
T
S
D
I
V
=
4
,
D
U
T
Y
=
5
0
%
0123456789101112131415
Tx
DIVIDER 0
DIVIDER 1
DIVIDER 2
CHANNEL
DIVIDER INPUT
SH = 0
PO = 0
SH = 0
PO = 1
SH = 0
PO = 2
1 × Tx
2 × Tx
06420-071
Figure 55. Effect of Coarse Phase Offset (or Delay)
Channel Dividers—LVDS/CMOS Outputs
Channel Divider 3 and Channel Divider 4 each drive a pair of
LVDS outputs, giving a total of four LVDS outputs (OUT6 to
OUT9). Alternatively, each of these LVDS differential outputs
can be configured individually as a pair (A and B) of CMOS
single-ended outputs, providing for up to eight CMOS outputs.
By default, the B output of each pair is off but can be turned on
as desired.
Channel Divider 3 and Channel Divider 4 each consist of two
cascaded, 2 to 32, frequency dividers. The channel frequency
division is D
X.1
× D
X.2
or up to 1024. Divide-by-1 is achieved by
bypassing one or both of these dividers. Both of the dividers
also have DCC enabled by default, but this function can be
disabled, if desired, by setting the DCCOFF bit of the channel.
A coarse phase offset or delay is also programmable (see the
Phase Offset or Coarse Time Delay (Divider 3 and Divider 4)
section). The channel dividers operate up to 1600 MHz. The
features and settings of the dividers are selected by programming
the appropriate setup and control registers (see Table 52 and
Table 53 through Table 62).
Table 39. Setting Division (D
X
) for Divider 3, Divider 4
1
Divider M N Bypass DCCOFF
3 3.1 0x199[7:4] 0x199[3:0] 0x19C[4] 0x19D[0]
3.2 0x19B[7:4] 0x19B[3:0] 0x19C[5] 0x19D[0]
4 4.1 0x19E[7:4] 0x19E[3:0] 0x1A1[4] 0x1A2[0]
4.2 0x1A0[7:4] 0x1A0[3:0] 0x1A1[5] 0x1A2[0]
1
Note that the value stored in the register = # of cycles minus 1.
Channel Frequency Division (Divider 3 and Divider 4)
The division for each channel divider is set by the bits in the
registers for the individual dividers (X.Y = 3.1, 3.2, 4.1, and 4.2)
Number of Low Cycles = M
X.Y
+ 1
Number of High Cycles = N
X.Y
+ 1
When both X.1 and X.2 are bypassed, D
X
= 1 × 1 = 1.
When only X.2 is bypassed, D
X
= (N
X.1
+ M
X.1
+ 2) × 1.
When both X.1 and X.2 are not bypassed, D
X
= (N
X.1
+ M
X.1
+ 2) ×
(N
X.2
+ M
X.2
+ 2).
By cascading the dividers, channel division up to 1024 can be
obtained. However, not all integer value divisions from 1 to
1024 are obtainable; only the values that are the product of the
separate divisions of the two dividers (D
X.1
× D
X.2
) can be realized.
If only one divider is needed when using Divider 3 and Divider 4,
use the first one (X.1) and bypass the second one (X.2). Do not
bypass X.1 and use X.2.