Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Functional Block Diagram
- Revision History
- Specifications
- Power Supply Requirements
- PLL Characteristics
- Clock Inputs
- Clock Outputs
- Timing Characteristics
- Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used)
- Clock Output Absolute Phase Noise (Internal VCO Used)
- Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Cleanup Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Generation Using External VCXO)
- Clock Output Additive Time Jitter (VCO Divider Not Used)
- Clock Output Additive Time Jitter (VCO Divider Used)
- Delay Block Additive Time Jitter
- Serial Control Port
- PD, RESET, and SYNC Pins
- LD, STATUS, and REFMON Pins
- Power Dissipation
- Timing Diagrams
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Detailed Block Diagram
- Theory of Operation
- Operational Configurations
- High Frequency Clock Distribution—CLK or External VCO > 1600 MHz
- Internal VCO and Clock Distribution
- Clock Distribution or External VCO < 1600 MHz
- Phase-Locked Loop (PLL)
- Configuration of the PLL
- Phase Frequency Detector (PFD)
- Charge Pump (CP)
- On-Chip VCO
- PLL External Loop Filter
- PLL Reference Inputs
- Reference Switchover
- Reference Divider R
- VCXO/VCO Feedback Divider N—P, A, B, R
- Digital Lock Detect (DLD)
- Clock Distribution
- Reset Modes
- Power-Down Modes
- Operational Configurations
- Serial Control Port
- Thermal Performance
- Register Map Overview
- Register Map Descriptions
- Applications Information
- Outline Dimensions
Data Sheet AD9516-1
Rev. C | Page 27 of 80
THEORY OF OPERATION
OPERATIONAL CONFIGURATIONS
The AD9516 can be configured in several ways. These
configurations must be set up by loading the control registers
(see Table 52 and Table 53 through Table 62). Each section
or function must be individually programmed by setting the
appropriate bits in the corresponding control register or registers.
High Frequency Clock Distribution—CLK or External
VCO > 1600 MHz
The AD9516 power-up default configuration has the PLL
powered off and the routing of the input set so that the
CLK/
CLK
input is connected to the distribution section
through the VCO divider (divide-by-2/ divide-by-3/divide-by-
4/divide-by-5/divide-by-6). This is a distribution only mode
that allows for an external input up to 2400 MHz (see Table 3).
The maximum frequency that can be applied to the channel
dividers is 1600 MHz; therefore, higher input frequencies must
be divided down before reaching the channel dividers. This
input routing can also be used for lower input frequencies, but
the minimum divide is 2 before the channel dividers.
When the PLL is enabled, this routing also allows the use of the
PLL with an external VCO or VCXO with a frequency of less
than 2400 MHz. In this configuration, the internal VCO is not
used and is powered off. The external VCO/VCXO feeds
directly into the prescaler.
The register settings shown in Table 21 are the default values of
these registers at power-up or after a reset operation. If the
contents of the registers are altered by prior programming after
power-up or reset, these registers can also be set intentionally to
these values.
After the appropriate register values are programmed,
Register 0x232 must be set to 0x01 for the values to take effect.
Table 21. Default Settings of Some PLL Registers
Register Function
0x010[1:0] = 01b PLL asynchronous power-down (PLL off ).
0x1E0[2:0] = 010b
Set VCO divider = 4.
0x1E1[0] = 0b Use the VCO divider.
0x1E1[1] = 0b CLK selected as the source.
When using the internal PLL with an external VCO, the PLL
must be turned on.
Table 22. Settings When Using an External VCO
Register Function
0x010[1:0] = 00b PLL normal operation (PLL on).
0x010 to 0x01D PLL settings. Select and enable a reference
input; set R, N (P, A, B), PFD polarity, and I
CP
,
according to the intended loop configuration.
0x1E1[1] = 0b CLK selected as the source.
An external VCO requires an external loop filter that must be
connected between CP and the tuning pin of the VCO. This
loop filter determines the loop bandwidth and stability of the
PLL. Make sure to select the proper PFD polarity for the VCO
being used.
Table 23. Setting the PFD Polarity
Register Function
0x010[7] = 0b PFD polarity positive (higher control
voltage produces higher frequency).
0x010[7] = 1b PFD polarity negative (higher control
voltage produces lower frequency).