Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Functional Block Diagram
- Revision History
- Specifications
- Power Supply Requirements
- PLL Characteristics
- Clock Inputs
- Clock Outputs
- Timing Characteristics
- Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used)
- Clock Output Absolute Phase Noise (Internal VCO Used)
- Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Cleanup Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Generation Using External VCXO)
- Clock Output Additive Time Jitter (VCO Divider Not Used)
- Clock Output Additive Time Jitter (VCO Divider Used)
- Delay Block Additive Time Jitter
- Serial Control Port
- PD, RESET, and SYNC Pins
- LD, STATUS, and REFMON Pins
- Power Dissipation
- Timing Diagrams
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Detailed Block Diagram
- Theory of Operation
- Operational Configurations
- High Frequency Clock Distribution—CLK or External VCO > 1600 MHz
- Internal VCO and Clock Distribution
- Clock Distribution or External VCO < 1600 MHz
- Phase-Locked Loop (PLL)
- Configuration of the PLL
- Phase Frequency Detector (PFD)
- Charge Pump (CP)
- On-Chip VCO
- PLL External Loop Filter
- PLL Reference Inputs
- Reference Switchover
- Reference Divider R
- VCXO/VCO Feedback Divider N—P, A, B, R
- Digital Lock Detect (DLD)
- Clock Distribution
- Reset Modes
- Power-Down Modes
- Operational Configurations
- Serial Control Port
- Thermal Performance
- Register Map Overview
- Register Map Descriptions
- Applications Information
- Outline Dimensions
AD9516-1 Data Sheet
Rev. C | Page 22 of 80
1600
800
1000
1200
1400
0 321
DIFFERENTIAL SWING (mV p-p)
FREQUENCY (GHz)
06420-020
Figure 25. LVPECL Differential Swing vs. Frequency
Using a Differential Probe Across the Output Pair
700
500
600
0 800
700600500400300
200100
DIFFERENTIAL SWING (mV p-p)
FREQUENCY (MHz)
06420-021
Figure 26. LVDS Differential Swing vs. Frequency
Using a Differential Probe Across the Output Pair
3
2
1
0
0 600500400300200100
OUTPUT SWING (V)
OUTPUT FREQUENCY (MHz)
C
L
= 2pF
C
L
= 10pF
C
L
= 20pF
06420-133
Figure 27. CMOS Output Swing vs. Frequency and Capacitive Load
–70
–80
–90
–100
–110
–120
–130
–140
–150
10k 100M10M
1M100k
PHASE NOISE (dBc/Hz)
FREQUENCY (Hz)
06420-023
Figure 28. Internal VCO Phase Noise (Absolute) Direct to LVPECL at 2650 MHz
–70
–80
–90
–100
–110
–120
–130
–140
–150
10k 100M10M
1M100k
PHASE NOISE (dBc/Hz)
FREQUENCY (Hz)
06420-024
Figure 29. Internal VCO Phase Noise (Absolute) Direct to LVPECL at 2475 MHz
–70
–80
–90
–100
–110
–120
–130
–140
–150
10k 100M
10M1M100k
PHASE NOISE (dBc/Hz)
FREQUENCY (Hz)
06420-025
Figure 30. Internal VCO Phase Noise (Absolute) Direct to LVPECL at 2300 MHz