Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Functional Block Diagram
- Revision History
- Specifications
- Power Supply Requirements
- PLL Characteristics
- Clock Inputs
- Clock Outputs
- Timing Characteristics
- Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used)
- Clock Output Absolute Phase Noise (Internal VCO Used)
- Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Cleanup Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Generation Using External VCXO)
- Clock Output Additive Time Jitter (VCO Divider Not Used)
- Clock Output Additive Time Jitter (VCO Divider Used)
- Delay Block Additive Time Jitter
- Serial Control Port
- PD, RESET, and SYNC Pins
- LD, STATUS, and REFMON Pins
- Power Dissipation
- Timing Diagrams
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Detailed Block Diagram
- Theory of Operation
- Operational Configurations
- High Frequency Clock Distribution—CLK or External VCO > 1600 MHz
- Internal VCO and Clock Distribution
- Clock Distribution or External VCO < 1600 MHz
- Phase-Locked Loop (PLL)
- Configuration of the PLL
- Phase Frequency Detector (PFD)
- Charge Pump (CP)
- On-Chip VCO
- PLL External Loop Filter
- PLL Reference Inputs
- Reference Switchover
- Reference Divider R
- VCXO/VCO Feedback Divider N—P, A, B, R
- Digital Lock Detect (DLD)
- Clock Distribution
- Reset Modes
- Power-Down Modes
- Operational Configurations
- Serial Control Port
- Thermal Performance
- Register Map Overview
- Register Map Descriptions
- Applications Information
- Outline Dimensions
Data Sheet AD9516-1
Rev. C | Page 21 of 80
1.0
0.6
0.2
–0.2
–0.6
–1.0
0 252015105
DIFFERENTIAL OUTPUT (V)
TIME (ns)
06420-014
Figure 19. LVPECL Output (Differential) at 100 MHz
1.0
0.6
0.2
–0.2
–0.6
–1.0
0 2
1
DIFFERENTIAL OUTPUT (V)
TIME (ns)
06420-015
Figure 20. LVPECL Output (Differential) at 1600 MHz
0.4
0.2
0
–0.2
–0.4
0 25201510
5
DIFFERENTIAL OUTPUT (V)
TIME (ns)
06420-016
Figure 21. LVDS Output (Differential) at 100 MHz
0.4
0.2
0
–0.2
–0.4
0 21
DIFFERENTIAL OUTPUT (V)
TIME (ns)
06420-017
Figure 22. LVDS Output (Differential) at 800 MHz
2.8
0.8
1.8
–0.2
0 8060 1004020
DIFFERENTIAL OUTPUT (V)
TIME (ns)
06420-018
Figure 23.CMOS Output at 25 MHz
2.8
0.8
1.8
–0.2
0
86 1210
42
OUTPUT (V)
TIME (ns)
06420-019
Figure 24. CMOS Output at 250 MHz