Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Functional Block Diagram
- Revision History
- Specifications
- Power Supply Requirements
- PLL Characteristics
- Clock Inputs
- Clock Outputs
- Timing Characteristics
- Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used)
- Clock Output Absolute Phase Noise (Internal VCO Used)
- Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Cleanup Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Generation Using External VCXO)
- Clock Output Additive Time Jitter (VCO Divider Not Used)
- Clock Output Additive Time Jitter (VCO Divider Used)
- Delay Block Additive Time Jitter
- Serial Control Port
- PD, RESET, and SYNC Pins
- LD, STATUS, and REFMON Pins
- Power Dissipation
- Timing Diagrams
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Detailed Block Diagram
- Theory of Operation
- Operational Configurations
- High Frequency Clock Distribution—CLK or External VCO > 1600 MHz
- Internal VCO and Clock Distribution
- Clock Distribution or External VCO < 1600 MHz
- Phase-Locked Loop (PLL)
- Configuration of the PLL
- Phase Frequency Detector (PFD)
- Charge Pump (CP)
- On-Chip VCO
- PLL External Loop Filter
- PLL Reference Inputs
- Reference Switchover
- Reference Divider R
- VCXO/VCO Feedback Divider N—P, A, B, R
- Digital Lock Detect (DLD)
- Clock Distribution
- Reset Modes
- Power-Down Modes
- Operational Configurations
- Serial Control Port
- Thermal Performance
- Register Map Overview
- Register Map Descriptions
- Applications Information
- Outline Dimensions

AD9516-1 Data Sheet
Rev. C | Page 20 of 80
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0.1 1 10010
PFD PHASE NOISE REFERRED TO PFD INPUT
(dBc/Hz)
PFD FREQUENCY (MHz)
06420-013
Figure 13. PFD Phase Noise Referred to PFD Input vs. PFD Frequency
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0 2.52.0
1.5
1.00.5
PLL FIGURE OF MERIT (dBc/Hz)
SLEW RATE (V/ns)
06420-136
Figure 14. PLL Figure of Merit (FOM) vs. Slew Rate at REFIN/
REFIN
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
2.3 2.4 2.5 2.6 2.7
VCO TUNING VOLTAGE (V)
FREQUENCY (GHz)
06420-138
Figure 15. VCO Tuning Voltage vs. Frequency
(Note that VCO calibration centers the dc tuning voltage
for the PLL setup that is active during calibration.)
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10
0
CENTER 122.88MHz SPAN 50MHz
5MHz/DIV
RELATIVE POWER (dB)
06420-137
Figure 16. PFD/CP Spurs; 122.88 MHz; PFD = 15.36 MHz;
LBW = 55 kHz; I
CP
= 4.8 mA; F
VCO
= 2.46 GHz
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10
0
CENTER 122.88MHz SPAN 1MHz100kHz/DIV
RELATIVE POWER (dB)
06420-135
Figure 17. Output Spectrum, LVPECL; 122.88 MHz; PFD = 15.36 MHz;
LBW = 55 kHz; I
CP
= 4.8 mA; F
VCO
= 2.46 GHz
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–40
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10
0
CENTER 122.88MHz SPAN 1MHz100kHz/DIV
RELATIVE POWER (dB)
06420-134
Figure 18. Output Spectrum, LVDS; 122.88 MHz; PFD = 15.36 MHz;
LBW = 55 kHz; I
CP
= 4.8 mA; F
VCO
= 2.46 GHz