Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Functional Block Diagram
- Revision History
- Specifications
- Power Supply Requirements
- PLL Characteristics
- Clock Inputs
- Clock Outputs
- Timing Characteristics
- Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used)
- Clock Output Absolute Phase Noise (Internal VCO Used)
- Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Cleanup Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Generation Using External VCXO)
- Clock Output Additive Time Jitter (VCO Divider Not Used)
- Clock Output Additive Time Jitter (VCO Divider Used)
- Delay Block Additive Time Jitter
- Serial Control Port
- PD, RESET, and SYNC Pins
- LD, STATUS, and REFMON Pins
- Power Dissipation
- Timing Diagrams
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Detailed Block Diagram
- Theory of Operation
- Operational Configurations
- High Frequency Clock Distribution—CLK or External VCO > 1600 MHz
- Internal VCO and Clock Distribution
- Clock Distribution or External VCO < 1600 MHz
- Phase-Locked Loop (PLL)
- Configuration of the PLL
- Phase Frequency Detector (PFD)
- Charge Pump (CP)
- On-Chip VCO
- PLL External Loop Filter
- PLL Reference Inputs
- Reference Switchover
- Reference Divider R
- VCXO/VCO Feedback Divider N—P, A, B, R
- Digital Lock Detect (DLD)
- Clock Distribution
- Reset Modes
- Power-Down Modes
- Operational Configurations
- Serial Control Port
- Thermal Performance
- Register Map Overview
- Register Map Descriptions
- Applications Information
- Outline Dimensions
Data Sheet AD9516-1
Rev. C | Page 19 of 80
TYPICAL PERFORMANCE CHARACTERISTICS
300
100
120
140
160
180
200
220
240
260
280
0 500 1000 1500 2000 2500
3000
CURRENT (mA)
FREQUENCY (MHz)
3 CHANNELS—6 LVPECL
3 CHANNELS—3 LVPECL
2 CHANNELS—2 LVPECL
1 CHANNEL—1 LVPECL
06420-007
Figure 7. Current vs. Frequency, Direct to Output, LVPECL Outputs
180
160
140
120
100
80
0 200 400 600 800
CURRENT (mA)
FREQUENCY (MHz)
1 CHANNEL—1 LVDS
2 CHANNELS—2 LVDS
2 CHANNELS—4 LVDS
06420-008
Figure 8. Current vs. Frequency—LVDS Outputs
(Includes Clock Distribution Current Draw)
240
200
160
220
180
140
120
100
80
0 250200
15010050
CURRENT (mA)
FREQUENCY (MHz)
1 CHANNEL—2 CMOS
1 CHANNEL—1 CMOS
2 CHANNEL—2 CMOS
2 CHANNEL—8 CMOS
06420-009
Figure 9. Current vs. Frequency—CMOS Outputs
65
35
40
45
50
55
60
2.3 2.72.62.52.4
K
VCO
(MHz/V)
VCO FREQUENCY (GHz)
06420-010
Figure 10. VCO K
VCO
vs. Frequency
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0 0.5 1.0 1.5 2.0
2.5 3.0
CURRENT FROM CP PIN (mA)
VOLTAGE ON CP PIN (V)
PUMP DOWN PUMP UP
06420-011
Figure 11. Charge Pump Characteristics at V
CP
= 3.3 V
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0 0.5 1.0
1.5 2.0 3.0 4.02.5 3.5 5.04.5
CURRENT FROM CP PIN (mA)
VOLTAGE ON CP PIN (V)
PUMP DOWN
PUMP UP
06420-012
Figure 12. Charge Pump Characteristics at V
CP
= 5.0 V