Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Functional Block Diagram
- Revision History
- Specifications
- Power Supply Requirements
- PLL Characteristics
- Clock Inputs
- Clock Outputs
- Timing Characteristics
- Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used)
- Clock Output Absolute Phase Noise (Internal VCO Used)
- Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Cleanup Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Generation Using External VCXO)
- Clock Output Additive Time Jitter (VCO Divider Not Used)
- Clock Output Additive Time Jitter (VCO Divider Used)
- Delay Block Additive Time Jitter
- Serial Control Port
- PD, RESET, and SYNC Pins
- LD, STATUS, and REFMON Pins
- Power Dissipation
- Timing Diagrams
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Detailed Block Diagram
- Theory of Operation
- Operational Configurations
- High Frequency Clock Distribution—CLK or External VCO > 1600 MHz
- Internal VCO and Clock Distribution
- Clock Distribution or External VCO < 1600 MHz
- Phase-Locked Loop (PLL)
- Configuration of the PLL
- Phase Frequency Detector (PFD)
- Charge Pump (CP)
- On-Chip VCO
- PLL External Loop Filter
- PLL Reference Inputs
- Reference Switchover
- Reference Divider R
- VCXO/VCO Feedback Divider N—P, A, B, R
- Digital Lock Detect (DLD)
- Clock Distribution
- Reset Modes
- Power-Down Modes
- Operational Configurations
- Serial Control Port
- Thermal Performance
- Register Map Overview
- Register Map Descriptions
- Applications Information
- Outline Dimensions
AD9516-1 Data Sheet
Rev. C | Page 16 of 80
ABSOLUTE MAXIMUM RATINGS
Table 18.
Parameter Rating
VS, VS_LVPECL to GND −0.3 V to +3.6 V
VCP to GND
−0.3 V to+5.8 V
REFIN,
REFIN
to GND −0.3 V to V
S
+ 0.3 V
REFIN to
REFIN
−3.3 V to +3.3 V
RSET to GND −0.3 V to V
S
+ 0.3 V
CPRSET to GND −0.3 V to V
S
+ 0.3 V
CLK,
CLK
to GND −0.3 V to V
S
+ 0.3 V
CLK to
CLK
−1.2 V to +1.2 V
SCLK, SDIO, SDO,
CS
to GND −0.3 V to V
S
+ 0.3 V
OUT0,
OUT0
, OUT1,
OUT1
, OUT2,
OUT2
,
OUT3,
OUT3
, OUT4,
OUT4
, OUT5,
OUT5
,
OUT6,
OUT6
, OUT7,
OUT7
, OUT8,
OUT8
,
OUT9,
OUT9
to GND
−0.3 V to V
S
+ 0.3 V
SYNC
to GND
−0.3 V to V
S
+ 0.3 V
REFMON, STATUS, LD to GND −0.3 V to V
S
+ 0.3 V
Junction Temperature
1
150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (10 sec) 300°C
1
See Table 19 for θ
JA
.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Table 19.
Package Type
1
θ
JA
Unit
64-Lead LFCSP 24 °C/W
1
Thermal impedance measurements were taken on a 4-layer board in still air
in accordance with EIA/JESD51-2.
ESD CAUTION