Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Functional Block Diagram
- Revision History
- Specifications
- Power Supply Requirements
- PLL Characteristics
- Clock Inputs
- Clock Outputs
- Timing Characteristics
- Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used)
- Clock Output Absolute Phase Noise (Internal VCO Used)
- Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Cleanup Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Generation Using External VCXO)
- Clock Output Additive Time Jitter (VCO Divider Not Used)
- Clock Output Additive Time Jitter (VCO Divider Used)
- Delay Block Additive Time Jitter
- Serial Control Port
- PD, RESET, and SYNC Pins
- LD, STATUS, and REFMON Pins
- Power Dissipation
- Timing Diagrams
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Detailed Block Diagram
- Theory of Operation
- Operational Configurations
- High Frequency Clock Distribution—CLK or External VCO > 1600 MHz
- Internal VCO and Clock Distribution
- Clock Distribution or External VCO < 1600 MHz
- Phase-Locked Loop (PLL)
- Configuration of the PLL
- Phase Frequency Detector (PFD)
- Charge Pump (CP)
- On-Chip VCO
- PLL External Loop Filter
- PLL Reference Inputs
- Reference Switchover
- Reference Divider R
- VCXO/VCO Feedback Divider N—P, A, B, R
- Digital Lock Detect (DLD)
- Clock Distribution
- Reset Modes
- Power-Down Modes
- Operational Configurations
- Serial Control Port
- Thermal Performance
- Register Map Overview
- Register Map Descriptions
- Applications Information
- Outline Dimensions
Data Sheet AD9516-1
Rev. C | Page 15 of 80
TIMING DIAGRAMS
CL
K
t
CMOS
t
CLK
t
LVDS
t
PECL
06420-060
Figure 2. CLK/
CLK
to Clock Output Timing, DIV = 1
DIFFERENTIAL
LVPECL
80%
20%
t
RP
t
FP
06420-061
Figure 3. LVPECL Timing, Differential
DIFFERENTIAL
LVDS
80%
20%
t
RL
t
FL
06420-062
Figure 4. LVDS Timing, Differential
SINGLE-ENDED
CMOS
10pF LOAD
80%
20%
t
RC
t
FC
06420-063
Figure 5. CMOS Timing, Single-Ended, 10 pF Load