Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Functional Block Diagram
- Revision History
- Specifications
- Power Supply Requirements
- PLL Characteristics
- Clock Inputs
- Clock Outputs
- Timing Characteristics
- Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used)
- Clock Output Absolute Phase Noise (Internal VCO Used)
- Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Cleanup Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Generation Using External VCXO)
- Clock Output Additive Time Jitter (VCO Divider Not Used)
- Clock Output Additive Time Jitter (VCO Divider Used)
- Delay Block Additive Time Jitter
- Serial Control Port
- PD, RESET, and SYNC Pins
- LD, STATUS, and REFMON Pins
- Power Dissipation
- Timing Diagrams
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Detailed Block Diagram
- Theory of Operation
- Operational Configurations
- High Frequency Clock Distribution—CLK or External VCO > 1600 MHz
- Internal VCO and Clock Distribution
- Clock Distribution or External VCO < 1600 MHz
- Phase-Locked Loop (PLL)
- Configuration of the PLL
- Phase Frequency Detector (PFD)
- Charge Pump (CP)
- On-Chip VCO
- PLL External Loop Filter
- PLL Reference Inputs
- Reference Switchover
- Reference Divider R
- VCXO/VCO Feedback Divider N—P, A, B, R
- Digital Lock Detect (DLD)
- Clock Distribution
- Reset Modes
- Power-Down Modes
- Operational Configurations
- Serial Control Port
- Thermal Performance
- Register Map Overview
- Register Map Descriptions
- Applications Information
- Outline Dimensions
Data Sheet AD9516-1
Rev. C | Page 13 of 80
PD
,
RESET
, AND
SYNC
PINS
Table 15.
Parameter Min Typ Max Unit Test Conditions/Comments
INPUT CHARACTERISTICS
These pins each have a 30 kΩ internal pull-up
resistor
Logic 1 Voltage 2.0 V
Logic 0 Voltage 0.8 V
Logic 1 Current 110 µA
Logic 0 Current 1 µA
Capacitance
2
pF
RESET
TIMING
Pulse Width Low 50 ns
SYNC
TIMING
Pulse Width Low 1.5 High speed
clock cycles
High speed clock is CLK input signal
LD, STATUS, AND REFMON PINS
Table 16.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
OUTPUT CHARACTERISTICS When selected as a digital output (CMOS); there are
other modes in which these pins are not CMOS
digital outputs; see Table 54, Register 0x017,
Register 0x01A, and Register 0x01B
Output Voltage High (V
OH
) 2.7 V
Output Voltage Low (V
OL
) 0.4 V
MAXIMUM TOGGLE RATE 100 MHz Applies when mux is set to any divider or counter
output or PFD up/down pulse; also applies in
analog lock detect mode; usually debug mode
only; beware that spurs may couple to output
when any of these pins are toggling
ANALOG LOCK DETECT
Capacitance 3 pF On-chip capacitance; used to calculate RC time
constant for analog lock detect readback; use a
pull-up resistor
REF1, REF2, AND VCO FREQUENCY STATUS MONITOR
Normal Range 1.02 MHz Frequency above which the monitor always
indicates the presence of the reference
Extended Range (REF1 and REF2 Only) 8 kHz Frequency above which the monitor always
indicates the presence of the reference
LD PIN COMPARATOR
Trip Point 1.6 V
Hysteresis 260 mV