Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Functional Block Diagram
- Revision History
- Specifications
- Power Supply Requirements
- PLL Characteristics
- Clock Inputs
- Clock Outputs
- Timing Characteristics
- Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used)
- Clock Output Absolute Phase Noise (Internal VCO Used)
- Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Cleanup Using Internal VCO)
- Clock Output Absolute Time Jitter (Clock Generation Using External VCXO)
- Clock Output Additive Time Jitter (VCO Divider Not Used)
- Clock Output Additive Time Jitter (VCO Divider Used)
- Delay Block Additive Time Jitter
- Serial Control Port
- PD, RESET, and SYNC Pins
- LD, STATUS, and REFMON Pins
- Power Dissipation
- Timing Diagrams
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Detailed Block Diagram
- Theory of Operation
- Operational Configurations
- High Frequency Clock Distribution—CLK or External VCO > 1600 MHz
- Internal VCO and Clock Distribution
- Clock Distribution or External VCO < 1600 MHz
- Phase-Locked Loop (PLL)
- Configuration of the PLL
- Phase Frequency Detector (PFD)
- Charge Pump (CP)
- On-Chip VCO
- PLL External Loop Filter
- PLL Reference Inputs
- Reference Switchover
- Reference Divider R
- VCXO/VCO Feedback Divider N—P, A, B, R
- Digital Lock Detect (DLD)
- Clock Distribution
- Reset Modes
- Power-Down Modes
- Operational Configurations
- Serial Control Port
- Thermal Performance
- Register Map Overview
- Register Map Descriptions
- Applications Information
- Outline Dimensions
AD9516-1 Data Sheet
Rev. C | Page 12 of 80
DELAY BLOCK ADDITIVE TIME JITTER
Table 13.
Parameter Min Typ Max Unit Test Conditions/Comments
DELAY BLOCK ADDITIVE TIME JITTER
1
Incremental additive jitter
100 MHz Output
Delay (1600 µA, 0x1C) Fine Adj. 000000 0.54 ps rms
Delay (1600 µA, 0x1C) Fine Adj. 101111 0.60 ps rms
Delay (800 µA, 0x1C) Fine Adj. 000000 0.65 ps rms
Delay (800 µA, 0x1C) Fine Adj. 101111 0.85 ps rms
Delay (800 µA, 0x4C) Fine Adj. 000000 0.79 ps rms
Delay (800 µA, 0x4C) Fine Adj. 101111 1.2 ps rms
Delay (400 µA, 0x4C) Fine Adj. 000000 1.2 ps rms
Delay (400 µA, 0x4C) Fine Adj. 101111 2.0 ps rms
Delay (200 µA, 0x1C) Fine Adj. 000000 1.3 ps rms
Delay (200 µA, 0x1C) Fine Adj. 101111
2.5
ps rms
Delay (200 µA, 0x4C) Fine Adj. 000000 1.9 ps rms
Delay (200 µA, 0x4C) Fine Adj. 101111 3.8 ps rms
1
This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter
should be added to this value using the root sum of the squares (RSS) method.
SERIAL CONTROL PORT
Table 14.
Parameter Min Typ Max Unit Test Conditions/Comments
CS
(INPUT)
CS
has an internal 30 kΩ pull-up resistor
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current 3 µA
Input Logic 0 Current 110 µA
Input Capacitance 2 pF
SCLK (INPUT) SCLK has an internal 30 kΩ pull-down resistor
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current 110 µA
Input Logic 0 Current 1 µA
Input Capacitance 2 pF
SDIO (WHEN INPUT)
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current
10
nA
Input Logic 0 Current 20 nA
Input Capacitance 2 pF
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage 2.7 V
Output Logic 0 Voltage 0.4 V
TIMING
Clock Rate (SCLK, 1/t
SCLK
) 25 MHz
Pulse Width High, t
HIGH
16 ns
Pulse Width Low, t
LOW
16 ns
SDIO to SCLK Setup, t
DS
2 ns
SCLK to SDIO Hold, t
DH
1.1
ns
SCLK to Valid SDIO and SDO, t
DV
8 ns
CS
to SCLK Setup and Hold, t
S
, t
H
2 ns
CS
Minimum Pulse Width High, t
PWH
3 ns