Datasheet

Data Sheet AD9516-0
Rev. C | Page 15 of 80
TIMING DIAGRAMS
CL
K
t
CMOS
t
CLK
t
LVDS
t
PECL
06419-060
Figure 2. CLK/
CLK
to Clock Output Timing, DIV = 1
DIFFERENTIAL
LVPECL
80%
20%
t
RP
t
FP
06419-061
Figure 3. LVPECL Timing, Differential
DIFFERENTIAL
LVDS
80%
20%
t
RL
t
FL
06419-062
Figure 4. LVDS Timing, Differential
SINGLE-ENDED
CMOS
10pF LOAD
80%
20%
t
RC
t
FC
06419-063
Figure 5. CMOS Timing, Single-Ended, 10 pF Load