Datasheet

Data Sheet AD9515
Rev. A | Page 9 of 28
Parameter Min Typ Max Unit Test Conditions/Comments
CMOS OUTPUT ADDITIVE TIME JITTER Delay off
CLK = 400 MHz 290 fs rms Calculated from SNR of ADC method
CMOS (OUT1) = 100 MHz
Divide = 4
CLK = 400 MHz 315 fs rms Calculated from SNR of ADC method
CMOS (OUT1) = 100 MHz
Divide = 4
LVPECL (OUT0) = 50 MHz Interferer
DELAY BLOCK ADDITIVE TIME JITTER
1
100 MHz output; incremental additive jitter
1
Delay FS = 1.5 ns Fine Adj. 00000 0.71 ps rms
Delay FS = 1.5 ns Fine Adj. 11111 1.2 ps rms
Delay FS = 5 ns Fine Adj. 00000 1.3 ps rms
Delay FS = 5 ns Fine Adj. 11111
2.7
ps rms
Delay FS = 10 ns Fine Adj. 00000 2.0 ps rms
Delay FS = 10 ns Fine Adj. 11111 2.8 ps rms
1
This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter
should be added to this value using the root sum of the squares (RSS) method.
SYNCB, VREF, AND SETUP PINS
Table 6.
Parameter Min Typ Max Unit Test Conditions/Comments
SYNCB
Logic High
2.7
V
Logic Low 0.40 V
Capacitance 2 pF
VREF
Output Voltage 0.62 V
S
0.76 V
S
V Minimum − maximum from 0 mA to 1 mA load
S0 TO S10
Levels
0 0.1 V
S
V
1/3 0.2 V
S
0.45 V
S
V
2/3 0.55 V
S
0.8 V
S
V
1 0.9 V
S
V