Datasheet

Data Sheet AD9515
Rev. A | Page 13 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1VS
2CLK
3CLKB
4VS
5SYNCB
6VREF
7S10
8S9
18 OUT1B
19 OUT1
20 VS
21 VS
22 OUT0B
23 OUT0
24 VS
17 VS
9S8
10S7
11S6
13S4
15S2
14S3
16S1
12S5
26
VS
27
DNC
28
DNC
29
VS
30
VS
25
S0
TOP VIEW
(Not to Scale)
AD9515
31
GND
32
RSET
05597-005
Figure 6. 32-Lead LFCSP Pin Configuration
05597-006
1
32
8
9
25
24
16
17
THE EXPOSED PADDLE
IS AN ELECTRICAL AND
THERMAL CONNECTION
EXPOSED PAD
(BOTTOM VIEW)
GND
Figure 7. Exposed Paddle
Note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to
function properly, the paddle must be soldered to a PCB land that functions as both a heat dissipation path as well as an electrical
ground (analog).
Table 9. Pin Function Descriptions
Pin No. Mnemonic Description
1, 4, 17, 20, 21, 24, 26, 29, 30 VS Power Supply (3.3 V).
2 CLK Clock Input.
3 CLKB Complementary Clock Input. Used in conjunction with CLK.
5 SYNCB Used to Synchronize the Outputs; Active Low Signal.
6
VREF
Provides 2/3 V
S
Reference Voltage for Use with Programming Pins S0 to S10.
25, 16, 15, 14, 13, 12, 11, 10, 9,
8, 7
S0 to S10 Programming Pins. These pins determine the operation of the AD9515; 4-state logic.
18 OUT1B Complementary LVDS/Inverted CMOS Output. Includes a delay block.
19 OUT1 LVDS/CMOS Output. Includes a delay block.
22 OUT0B Complementary LVPECL Output.
23 OUT0 LVPECL Output.
27, 28 DNC Do Not Connect.
31, Exposed Paddle GND Ground. The exposed paddle on the back of the chip is also GND.
32 RSET Current Sets Resistor to Ground. Nominal value = 4.12 kΩ.