Datasheet

AD9514
Rev. 0 | Page 9 of 28
Parameter Min Typ Max Unit Test Conditions/Comments
CLK = 400 MHz 350 fs rms Calculated from SNR of ADC method
LVDS (OUT2) = 100 MHz
Divide = 4
Both LVPECL = 50 MHz Interferer(s)
CMOS OUTPUT ADDITIVE TIME JITTER Delay off
CLK = 400 MHz 290 fs rms Calculated from SNR of ADC method
CMOS (OUT2) = 100 MHz OUT0 at same frequency; OUT1 off
Divide = 4
CLK = 400 MHz 315 fs rms Calculated from SNR of ADC method
CMOS (OUT2) = 100 MHz
Divide = 4
Both LVPECL = 50 MHz Interferer(s)
DELAY BLOCK ADDITIVE TIME JITTER
1
100 MHz output; incremental additive jitter
Delay FS = 1.5 ns Fine Adj. 00000 0.71 ps rms
Delay FS = 1.5 ns Fine Adj. 11111 1.2 ps rms
Delay FS = 5 ns Fine Adj. 00000 1.3 ps rms
Delay FS = 5 ns Fine Adj. 11111 2.7 ps rms
Delay FS = 10 ns Fine Adj. 00000 2.0 ps rms
Delay FS = 10 ns Fine Adj. 11111 2.8 ps rms
1
This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter
should be added to this value using the root sum of the squares (RSS) method.